adc_1.hier_info

用verilog编程实现的基于FPGA的AD数据采集程序

|adc_1
clk => flag.CLK
clk => add[2]~reg0.CLK
clk => add[1]~reg0.CLK
clk => add[0]~reg0.CLK
clk => control~reg0.CLK
clk => beg.CLK
f_r => always0~0.IN1
f_r => flag~0.DATAA
reset => beg~3.OUTPUTSELECT
reset => flag~3.OUTPUTSELECT
reset => add~10.OUTPUTSELECT
reset => add~11.OUTPUTSELECT
reset => add~12.OUTPUTSELECT
reset => control~reg0.ENA
add[0] <= add[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[1] <= add[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[2] <= add[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
control <= control~reg0.DB_MAX_OUTPUT_PORT_TYPE