adc_1.fit.eqn

用verilog编程实现的基于FPGA的AD数据采集程序

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--A1L4Q is add[0]~reg0 at LC4_B33
--operation mode is normal

A1L4Q_lut_out = A1L11 & (A1L4Q $ flag $ f_r);
A1L4Q = DFFEA(A1L4Q_lut_out, GLOBAL(clk), , , , , );

--A1L3Q is add[0]~336 at LC4_B33
--operation mode is normal

A1L3Q = A1L4Q;


--A1L7Q is add[1]~reg0 at LC7_B34
--operation mode is normal

A1L7Q_lut_out = beg & reset & (A1L7Q $ A1L21);
A1L7Q = DFFEA(A1L7Q_lut_out, GLOBAL(clk), , , , , );

--A1L6Q is add[1]~337 at LC7_B34
--operation mode is normal

A1L6Q = A1L7Q;


--A1L01Q is add[2]~reg0 at LC5_B34
--operation mode is normal

A1L01Q_lut_out = A1L11 & (A1L01Q $ (A1L7Q & A1L21));
A1L01Q = DFFEA(A1L01Q_lut_out, GLOBAL(clk), , , , , );

--A1L9Q is add[2]~338 at LC5_B34
--operation mode is normal

A1L9Q = A1L01Q;


--A1L42Q is control~reg0 at LC1_B34
--operation mode is normal

A1L42Q_lut_out = beg & (A1L12 # !A1L51);
A1L42Q = DFFEA(A1L42Q_lut_out, GLOBAL(clk), , , reset, , );

--A1L22Q is control~66 at LC1_B34
--operation mode is normal

A1L22Q = A1L42Q;


--beg is beg at LC3_B34
--operation mode is normal

beg_lut_out = reset;
beg = DFFEA(beg_lut_out, GLOBAL(clk), , , , , );

--A1L81Q is beg~7 at LC3_B34
--operation mode is normal

A1L81Q = beg;


--A1L11 is add~331 at LC6_B34
--operation mode is normal

A1L11 = beg & reset;

--A1L31 is add~339 at LC6_B34
--operation mode is normal

A1L31 = beg & reset;


--flag is flag at LC1_B33
--operation mode is normal

flag_lut_out = reset & (A1L72 & f_r # !A1L72 & (flag));
flag = DFFEA(flag_lut_out, GLOBAL(clk), , , , , );

--A1L82Q is flag~227 at LC1_B33
--operation mode is normal

A1L82Q = flag;


--A1L21 is add~333 at LC5_B33
--operation mode is normal

A1L21 = A1L4Q & (flag $ f_r);

--A1L41 is add~340 at LC5_B33
--operation mode is normal

A1L41 = A1L4Q & (flag $ f_r);


--A1L72 is flag~225 at LC2_B34
--operation mode is normal

A1L72 = beg & (!A1L01Q # !A1L7Q # !A1L4Q);

--A1L92 is flag~228 at LC2_B34
--operation mode is normal

A1L92 = beg & (!A1L01Q # !A1L7Q # !A1L4Q);


--A1L12 is control~65 at LC4_B34
--operation mode is normal

A1L12 = A1L42Q & A1L4Q & A1L7Q & A1L01Q;

--A1L32 is control~67 at LC4_B34
--operation mode is normal

A1L32 = A1L42Q & A1L4Q & A1L7Q & A1L01Q;


--A1L51 is always0~0 at LC7_B33
--operation mode is normal

A1L51 = flag $ f_r;

--A1L61 is always0~6 at LC7_B33
--operation mode is normal

A1L61 = flag $ f_r;


--f_r is f_r at PIN_182
--operation mode is input

f_r = INPUT();


--clk is clk at PIN_79
--operation mode is input

clk = INPUT();


--reset is reset at PIN_184
--operation mode is input

reset = INPUT();


--add[0] is add[0] at PIN_144
--operation mode is output

add[0] = OUTPUT(A1L4Q);


--add[1] is add[1] at PIN_142
--operation mode is output

add[1] = OUTPUT(A1L7Q);


--add[2] is add[2] at PIN_143
--operation mode is output

add[2] = OUTPUT(A1L01Q);


--control is control at PIN_11
--operation mode is output

control = OUTPUT(A1L42Q);