adc_1.tan.rpt

用verilog编程实现的基于FPGA的AD数据采集程序

+-------+--------------+------------+-------+--------------+----------+
; N/A   ; None         ; 3.300 ns   ; reset ; add[0]~reg0  ; clk      ;
; N/A   ; None         ; 3.000 ns   ; f_r   ; add[1]~reg0  ; clk      ;
; N/A   ; None         ; 3.000 ns   ; f_r   ; add[2]~reg0  ; clk      ;
; N/A   ; None         ; 3.000 ns   ; f_r   ; control~reg0 ; clk      ;
; N/A   ; None         ; 2.900 ns   ; reset ; add[2]~reg0  ; clk      ;
; N/A   ; None         ; 2.000 ns   ; reset ; flag         ; clk      ;
; N/A   ; None         ; 1.900 ns   ; reset ; add[1]~reg0  ; clk      ;
; N/A   ; None         ; 1.900 ns   ; f_r   ; flag         ; clk      ;
; N/A   ; None         ; 1.800 ns   ; reset ; control~reg0 ; clk      ;
; N/A   ; None         ; 1.700 ns   ; reset ; beg          ; clk      ;
; N/A   ; None         ; 1.700 ns   ; f_r   ; add[0]~reg0  ; clk      ;
+-------+--------------+------------+-------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.900 ns   ; add[0]~reg0  ; add[0]  ; clk        ;
; N/A   ; None         ; 6.800 ns   ; add[2]~reg0  ; add[2]  ; clk        ;
; N/A   ; None         ; 6.800 ns   ; add[1]~reg0  ; add[1]  ; clk        ;
; N/A   ; None         ; 6.500 ns   ; control~reg0 ; control ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; -0.800 ns ; reset ; beg          ; clk      ;
; N/A           ; None        ; -0.800 ns ; f_r   ; add[0]~reg0  ; clk      ;
; N/A           ; None        ; -0.900 ns ; reset ; control~reg0 ; clk      ;
; N/A           ; None        ; -1.000 ns ; reset ; add[1]~reg0  ; clk      ;
; N/A           ; None        ; -1.000 ns ; f_r   ; flag         ; clk      ;
; N/A           ; None        ; -1.100 ns ; reset ; flag         ; clk      ;
; N/A           ; None        ; -2.000 ns ; reset ; add[2]~reg0  ; clk      ;
; N/A           ; None        ; -2.100 ns ; f_r   ; add[1]~reg0  ; clk      ;
; N/A           ; None        ; -2.100 ns ; f_r   ; add[2]~reg0  ; clk      ;
; N/A           ; None        ; -2.100 ns ; f_r   ; control~reg0 ; clk      ;
; N/A           ; None        ; -2.400 ns ; reset ; add[0]~reg0  ; clk      ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Dec 06 16:58:17 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adc_1 -c adc_1
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 294.12 MHz between source register "add[0]~reg0" and destination register "flag" (period= 3.4 ns)
    Info: + Longest register to register delay is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add[0]~reg0'
        Info: 2: + IC(0.800 ns) + CELL(0.700 ns) = 1.500 ns; Loc. = LC2_B34; Fanout = 1; COMB Node = 'flag~225'
        Info: 3: + IC(0.800 ns) + CELL(0.100 ns) = 2.400 ns; Loc. = LC1_B33; Fanout = 4; REG Node = 'flag'
        Info: Total cell delay = 0.800 ns ( 33.33 % )
        Info: Total interconnect delay = 1.600 ns ( 66.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC1_B33; Fanout = 4; REG Node = 'flag'
            Info: Total cell delay = 0.300 ns ( 27.27 % )
            Info: Total interconnect delay = 0.800 ns ( 72.73 % )
        Info: - Longest clock path from clock "clk" to source register is 1.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add[0]~reg0'
            Info: Total cell delay = 0.300 ns ( 27.27 % )
            Info: Total interconnect delay = 0.800 ns ( 72.73 % )
    Info: + Micro clock to output delay of source is 0.600 ns
    Info: + Micro setup delay of destination is 0.400 ns
Info: tsu for register "add[0]~reg0" (data pin = "reset", clock pin = "clk") is 3.300 ns
    Info: + Longest pin to register delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(2.000 ns) + CELL(0.500 ns) = 2.800 ns; Loc. = LC6_B34; Fanout = 2; COMB Node = 'add~331'
        Info: 3: + IC(0.800 ns) + CELL(0.400 ns) = 4.000 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add[0]~reg0'
        Info: Total cell delay = 1.200 ns ( 30.00 % )
        Info: Total interconnect delay = 2.800 ns ( 70.00 % )
    Info: + Micro setup delay of destination is 0.400 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add[0]~reg0'
        Info: Total cell delay = 0.300 ns ( 27.27 % )
        Info: Total interconnect delay = 0.800 ns ( 72.73 % )
Info: tco from clock "clk" to destination pin "add[0]" through register "add[0]~reg0" is 6.900 ns
    Info: + Longest clock path from clock "clk" to source register is 1.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add[0]~reg0'
        Info: Total cell delay = 0.300 ns ( 27.27 % )
        Info: Total interconnect delay = 0.800 ns ( 72.73 % )
    Info: + Micro clock to output delay of source is 0.600 ns
    Info: + Longest register to pin delay is 5.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B33; Fanout = 5; REG Node = 'add[0]~reg0'
        Info: 2: + IC(1.000 ns) + CELL(4.200 ns) = 5.200 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'add[0]'
        Info: Total cell delay = 4.200 ns ( 80.77 % )
        Info: Total interconnect delay = 1.000 ns ( 19.23 % )
Info: th for register "beg" (data pin = "reset", clock pin = "clk") is -0.800 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC3_B34; Fanout = 4; REG Node = 'beg'
        Info: Total cell delay = 0.300 ns ( 27.27 % )
        Info: Total interconnect delay = 0.800 ns ( 72.73 % )
    Info: + Micro hold delay of destination is 0.500 ns
    Info: - Shortest pin to register delay is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(2.000 ns) + CELL(0.100 ns) = 2.400 ns; Loc. = LC3_B34; Fanout = 4; REG Node = 'beg'
        Info: Total cell delay = 0.400 ns ( 16.67 % )
        Info: Total interconnect delay = 2.000 ns ( 83.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Dec 06 16:58:19 2007
    Info: Elapsed time: 00:00:02