adc_3.map.summary

用verilog编程实现的基于FPGA的AD数据采集程序

Flow Status : Successful - Thu Dec 06 16:48:39 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : adc_3
Top-level Entity Name : adc_3
Family : ACEX1K
Device : EP1K100QC208-1
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 6
Total pins : 26
Total memory bits : 96
Total PLLs : 0