adc_3.map.qmsg

用verilog编程实现的基于FPGA的AD数据采集程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 06 16:48:38 2007 " "Info: Processing started: Thu Dec 06 16:48:38 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adc_3 -c adc_3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc_3 -c adc_3" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc_3.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file adc_3.v" { { "Info" "ISGN_ENTITY_NAME" "1 adc_3 " "Info: Found entity 1: adc_3" {  } { { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adc_3 " "Info: Elaborating entity \"adc_3\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTDPRAM_INFERRED" "mema~0 8 12 " "Info: Inferred altdpram megafunction (NUMWORDS=8, WIDTH=12) from the following logic: \"mema~0\"" {  } { { "adc_3.v" "mema~0" { Text "F:/adc_3/adc_3.v" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altdpram " "Info: Found entity 1: altdpram" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 164 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altdpram:mema_rtl_0 " "Info: Issued messages during elaboration of megafunction \"altdpram:mema_rtl_0\"" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_TOP_EMPTY_CONTENT_FILENAME" "" "Warning: Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified -- setting initial contents to 0" { { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[11\] " "Warning: RAM name is \"segment\[0\]\[11\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[10\] " "Warning: RAM name is \"segment\[0\]\[10\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[9\] " "Warning: RAM name is \"segment\[0\]\[9\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[8\] " "Warning: RAM name is \"segment\[0\]\[8\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[7\] " "Warning: RAM name is \"segment\[0\]\[7\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[6\] " "Warning: RAM name is \"segment\[0\]\[6\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[5\] " "Warning: RAM name is \"segment\[0\]\[5\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[4\] " "Warning: RAM name is \"segment\[0\]\[4\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[3\] " "Warning: RAM name is \"segment\[0\]\[3\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[2\] " "Warning: RAM name is \"segment\[0\]\[2\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[1\] " "Warning: RAM name is \"segment\[0\]\[1\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0} { "Warning" "WCDB_SGATE_CDB_SUB_EMPTY_CONTENT_FILENAME" "segment\[0\]\[0\] " "Warning: RAM name is \"segment\[0\]\[0\]\"" {  } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 278 14 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "44 " "Info: Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "14 " "Info: Implemented 14 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "6 " "Info: Implemented 6 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 06 16:48:39 2007 " "Info: Processing ended: Thu Dec 06 16:48:39 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}