📄 adc_3.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "ad_sts memory altdpram:mema_rtl_0\|q\[11\]~reg_ra0 memory altdpram:mema_rtl_0\|q\[11\] 196.08 MHz 5.1 ns Internal " "Info: Clock \"ad_sts\" has Internal fmax of 196.08 MHz between source memory \"altdpram:mema_rtl_0\|q\[11\]~reg_ra0\" and destination memory \"altdpram:mema_rtl_0\|q\[11\]\" (period= 5.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altdpram:mema_rtl_0\|q\[11\]~reg_ra0 1 MEM EC12_A 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC12_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[11\]~reg_ra0'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { altdpram:mema_rtl_0|q[11]~reg_ra0 } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns altdpram:mema_rtl_0\|q\[11\]~mem_cell_ra0 2 MEM EC12_A 1 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = EC12_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[11\]~mem_cell_ra0'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "4.000 ns" { altdpram:mema_rtl_0|q[11]~reg_ra0 altdpram:mema_rtl_0|q[11]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 4.000 ns altdpram:mema_rtl_0\|q\[11\] 3 MEM EC12_A 1 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 4.000 ns; Loc. = EC12_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[11\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "0.000 ns" { altdpram:mema_rtl_0|q[11]~mem_cell_ra0 altdpram:mema_rtl_0|q[11] } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "4.000 ns" { altdpram:mema_rtl_0|q[11]~reg_ra0 altdpram:mema_rtl_0|q[11]~mem_cell_ra0 altdpram:mema_rtl_0|q[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { altdpram:mema_rtl_0|q[11]~reg_ra0 altdpram:mema_rtl_0|q[11]~mem_cell_ra0 altdpram:mema_rtl_0|q[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 4.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts destination 1.100 ns + Shortest memory " "Info: + Shortest clock path from clock \"ad_sts\" to destination memory is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns ad_sts 1 CLK PIN_79 123 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 123; CLK Node = 'ad_sts'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { ad_sts } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns altdpram:mema_rtl_0\|q\[11\] 2 MEM EC12_A 1 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = EC12_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[11\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "0.800 ns" { ad_sts altdpram:mema_rtl_0|q[11] } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[11] } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts source 1.100 ns - Longest memory " "Info: - Longest clock path from clock \"ad_sts\" to source memory is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns ad_sts 1 CLK PIN_79 123 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 123; CLK Node = 'ad_sts'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { ad_sts } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns altdpram:mema_rtl_0\|q\[11\]~reg_ra0 2 MEM EC12_A 1 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = EC12_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[11\]~reg_ra0'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "0.800 ns" { ad_sts altdpram:mema_rtl_0|q[11]~reg_ra0 } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[11]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[11]~reg_ra0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[11] } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[11]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[11]~reg_ra0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" { } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "4.000 ns" { altdpram:mema_rtl_0|q[11]~reg_ra0 altdpram:mema_rtl_0|q[11]~mem_cell_ra0 altdpram:mema_rtl_0|q[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { altdpram:mema_rtl_0|q[11]~reg_ra0 altdpram:mema_rtl_0|q[11]~mem_cell_ra0 altdpram:mema_rtl_0|q[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 4.000ns 0.000ns } } } { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[11] } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[11]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[11]~reg_ra0 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "altdpram:mema_rtl_0\|q\[9\]~reg_in data_in\[9\] ad_sts 4.400 ns memory " "Info: tsu for memory \"altdpram:mema_rtl_0\|q\[9\]~reg_in\" (data pin = \"data_in\[9\]\", clock pin = \"ad_sts\") is 4.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest pin memory " "Info: + Longest pin to memory delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns data_in\[9\] 1 PIN PIN_102 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_102; Fanout = 1; PIN Node = 'data_in\[9\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { data_in[9] } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.000 ns) 4.700 ns altdpram:mema_rtl_0\|q\[9\]~reg_in 2 MEM EC13_A 1 " "Info: 2: + IC(2.700 ns) + CELL(0.000 ns) = 4.700 ns; Loc. = EC13_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[9\]~reg_in'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "2.700 ns" { data_in[9] altdpram:mema_rtl_0|q[9]~reg_in } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 42.55 % " "Info: Total cell delay = 2.000 ns ( 42.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 57.45 % " "Info: Total interconnect delay = 2.700 ns ( 57.45 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "4.700 ns" { data_in[9] altdpram:mema_rtl_0|q[9]~reg_in } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { data_in[9] data_in[9]~out altdpram:mema_rtl_0|q[9]~reg_in } { 0.000ns 0.000ns 2.700ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts destination 1.100 ns - Shortest memory " "Info: - Shortest clock path from clock \"ad_sts\" to destination memory is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns ad_sts 1 CLK PIN_79 123 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 123; CLK Node = 'ad_sts'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { ad_sts } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns altdpram:mema_rtl_0\|q\[9\]~reg_in 2 MEM EC13_A 1 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = EC13_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[9\]~reg_in'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "0.800 ns" { ad_sts altdpram:mema_rtl_0|q[9]~reg_in } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[9]~reg_in } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[9]~reg_in } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "4.700 ns" { data_in[9] altdpram:mema_rtl_0|q[9]~reg_in } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.700 ns" { data_in[9] data_in[9]~out altdpram:mema_rtl_0|q[9]~reg_in } { 0.000ns 0.000ns 2.700ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[9]~reg_in } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[9]~reg_in } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ad_sts data_out\[8\] altdpram:mema_rtl_0\|q\[8\] 9.000 ns memory " "Info: tco from clock \"ad_sts\" to destination pin \"data_out\[8\]\" through memory \"altdpram:mema_rtl_0\|q\[8\]\" is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts source 1.100 ns + Longest memory " "Info: + Longest clock path from clock \"ad_sts\" to source memory is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns ad_sts 1 CLK PIN_79 123 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 123; CLK Node = 'ad_sts'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { ad_sts } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns altdpram:mema_rtl_0\|q\[8\] 2 MEM EC5_A 1 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = EC5_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[8\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "0.800 ns" { ad_sts altdpram:mema_rtl_0|q[8] } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[8] } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" { } { { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.600 ns + Longest memory pin " "Info: + Longest memory to pin delay is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns altdpram:mema_rtl_0\|q\[8\] 1 MEM EC5_A 1 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = EC5_A; Fanout = 1; MEM Node = 'altdpram:mema_rtl_0\|q\[8\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { altdpram:mema_rtl_0|q[8] } "NODE_NAME" } "" } } { "altdpram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 176 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.200 ns) 7.600 ns data_out\[8\] 2 PIN PIN_45 0 " "Info: 2: + IC(3.200 ns) + CELL(4.200 ns) = 7.600 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'data_out\[8\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "7.400 ns" { altdpram:mema_rtl_0|q[8] data_out[8] } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 5 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.400 ns 57.89 % " "Info: Total cell delay = 4.400 ns ( 57.89 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns 42.11 % " "Info: Total interconnect delay = 3.200 ns ( 42.11 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "7.600 ns" { altdpram:mema_rtl_0|q[8] data_out[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.600 ns" { altdpram:mema_rtl_0|q[8] data_out[8] } { 0.000ns 3.200ns } { 0.200ns 4.200ns } } } } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts altdpram:mema_rtl_0|q[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out altdpram:mema_rtl_0|q[8] } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "7.600 ns" { altdpram:mema_rtl_0|q[8] data_out[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.600 ns" { altdpram:mema_rtl_0|q[8] data_out[8] } { 0.000ns 3.200ns } { 0.200ns 4.200ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "num\[0\] sel ad_sts -0.300 ns register " "Info: th for register \"num\[0\]\" (data pin = \"sel\", clock pin = \"ad_sts\") is -0.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ad_sts destination 1.100 ns + Longest register " "Info: + Longest clock path from clock \"ad_sts\" to destination register is 1.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns ad_sts 1 CLK PIN_79 123 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_79; Fanout = 123; CLK Node = 'ad_sts'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { ad_sts } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 1.100 ns num\[0\] 2 REG LC5_A26 18 " "Info: 2: + IC(0.800 ns) + CELL(0.000 ns) = 1.100 ns; Loc. = LC5_A26; Fanout = 18; REG Node = 'num\[0\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "0.800 ns" { ad_sts num[0] } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.300 ns 27.27 % " "Info: Total cell delay = 0.300 ns ( 27.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 72.73 % " "Info: Total interconnect delay = 0.800 ns ( 72.73 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts num[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out num[0] } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.500 ns + " "Info: + Micro hold delay of destination is 0.500 ns" { } { { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns sel 1 PIN PIN_184 63 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 63; PIN Node = 'sel'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "" { sel } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.200 ns) 1.900 ns num\[0\] 2 REG LC5_A26 18 " "Info: 2: + IC(1.400 ns) + CELL(0.200 ns) = 1.900 ns; Loc. = LC5_A26; Fanout = 18; REG Node = 'num\[0\]'" { } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.600 ns" { sel num[0] } "NODE_NAME" } "" } } { "adc_3.v" "" { Text "F:/adc_3/adc_3.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns 26.32 % " "Info: Total cell delay = 0.500 ns ( 26.32 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 73.68 % " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" { } { } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.900 ns" { sel num[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { sel sel~out num[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.300ns 0.200ns } } } } 0} } { { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.100 ns" { ad_sts num[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.100 ns" { ad_sts ad_sts~out num[0] } { 0.000ns 0.000ns 0.800ns } { 0.000ns 0.300ns 0.000ns } } } { "F:/adc_3/db/adc_3_cmp.qrpt" "" { Report "F:/adc_3/db/adc_3_cmp.qrpt" Compiler "adc_3" "UNKNOWN" "V1" "F:/adc_3/db/adc_3.quartus_db" { Floorplan "F:/adc_3/" "" "1.900 ns" { sel num[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.900 ns" { sel sel~out num[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.300ns 0.200ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 06 16:48:59 2007 " "Info: Processing ended: Thu Dec 06 16:48:59 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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