adc_3.fit.eqn

用verilog编程实现的基于FPGA的AD数据采集程序

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--B1_q[0] is altdpram:mema_rtl_0|q[0] at EC7_A
B1_q[0]_data_in = data_in[0];
B1_q[0]_write_enable = sel;
B1_q[0]_clock_0 = !GLOBAL(ad_sts);
B1_q[0]_clock_1 = !GLOBAL(ad_sts);
B1_q[0]_clock_enable_1 = sel;
B1_q[0]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[0]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[0] = MEMORY_SEGMENT(B1_q[0]_data_in, B1_q[0]_write_enable, B1_q[0]_clock_0, B1_q[0]_clock_1, , , B1_q[0]_clock_enable_1, VCC, B1_q[0]_write_address, B1_q[0]_read_address);


--B1_q[1] is altdpram:mema_rtl_0|q[1] at EC10_A
B1_q[1]_data_in = data_in[1];
B1_q[1]_write_enable = sel;
B1_q[1]_clock_0 = !GLOBAL(ad_sts);
B1_q[1]_clock_1 = !GLOBAL(ad_sts);
B1_q[1]_clock_enable_1 = sel;
B1_q[1]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[1]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[1] = MEMORY_SEGMENT(B1_q[1]_data_in, B1_q[1]_write_enable, B1_q[1]_clock_0, B1_q[1]_clock_1, , , B1_q[1]_clock_enable_1, VCC, B1_q[1]_write_address, B1_q[1]_read_address);


--B1_q[2] is altdpram:mema_rtl_0|q[2] at EC2_A
B1_q[2]_data_in = data_in[2];
B1_q[2]_write_enable = sel;
B1_q[2]_clock_0 = !GLOBAL(ad_sts);
B1_q[2]_clock_1 = !GLOBAL(ad_sts);
B1_q[2]_clock_enable_1 = sel;
B1_q[2]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[2]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[2] = MEMORY_SEGMENT(B1_q[2]_data_in, B1_q[2]_write_enable, B1_q[2]_clock_0, B1_q[2]_clock_1, , , B1_q[2]_clock_enable_1, VCC, B1_q[2]_write_address, B1_q[2]_read_address);


--B1_q[3] is altdpram:mema_rtl_0|q[3] at EC9_A
B1_q[3]_data_in = data_in[3];
B1_q[3]_write_enable = sel;
B1_q[3]_clock_0 = !GLOBAL(ad_sts);
B1_q[3]_clock_1 = !GLOBAL(ad_sts);
B1_q[3]_clock_enable_1 = sel;
B1_q[3]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[3]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[3] = MEMORY_SEGMENT(B1_q[3]_data_in, B1_q[3]_write_enable, B1_q[3]_clock_0, B1_q[3]_clock_1, , , B1_q[3]_clock_enable_1, VCC, B1_q[3]_write_address, B1_q[3]_read_address);


--B1_q[4] is altdpram:mema_rtl_0|q[4] at EC6_A
B1_q[4]_data_in = data_in[4];
B1_q[4]_write_enable = sel;
B1_q[4]_clock_0 = !GLOBAL(ad_sts);
B1_q[4]_clock_1 = !GLOBAL(ad_sts);
B1_q[4]_clock_enable_1 = sel;
B1_q[4]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[4]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[4] = MEMORY_SEGMENT(B1_q[4]_data_in, B1_q[4]_write_enable, B1_q[4]_clock_0, B1_q[4]_clock_1, , , B1_q[4]_clock_enable_1, VCC, B1_q[4]_write_address, B1_q[4]_read_address);


--B1_q[5] is altdpram:mema_rtl_0|q[5] at EC11_A
B1_q[5]_data_in = data_in[5];
B1_q[5]_write_enable = sel;
B1_q[5]_clock_0 = !GLOBAL(ad_sts);
B1_q[5]_clock_1 = !GLOBAL(ad_sts);
B1_q[5]_clock_enable_1 = sel;
B1_q[5]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[5]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[5] = MEMORY_SEGMENT(B1_q[5]_data_in, B1_q[5]_write_enable, B1_q[5]_clock_0, B1_q[5]_clock_1, , , B1_q[5]_clock_enable_1, VCC, B1_q[5]_write_address, B1_q[5]_read_address);


--B1_q[6] is altdpram:mema_rtl_0|q[6] at EC4_A
B1_q[6]_data_in = data_in[6];
B1_q[6]_write_enable = sel;
B1_q[6]_clock_0 = !GLOBAL(ad_sts);
B1_q[6]_clock_1 = !GLOBAL(ad_sts);
B1_q[6]_clock_enable_1 = sel;
B1_q[6]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[6]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[6] = MEMORY_SEGMENT(B1_q[6]_data_in, B1_q[6]_write_enable, B1_q[6]_clock_0, B1_q[6]_clock_1, , , B1_q[6]_clock_enable_1, VCC, B1_q[6]_write_address, B1_q[6]_read_address);


--B1_q[7] is altdpram:mema_rtl_0|q[7] at EC16_A
B1_q[7]_data_in = data_in[7];
B1_q[7]_write_enable = sel;
B1_q[7]_clock_0 = !GLOBAL(ad_sts);
B1_q[7]_clock_1 = !GLOBAL(ad_sts);
B1_q[7]_clock_enable_1 = sel;
B1_q[7]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[7]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[7] = MEMORY_SEGMENT(B1_q[7]_data_in, B1_q[7]_write_enable, B1_q[7]_clock_0, B1_q[7]_clock_1, , , B1_q[7]_clock_enable_1, VCC, B1_q[7]_write_address, B1_q[7]_read_address);


--B1_q[8] is altdpram:mema_rtl_0|q[8] at EC5_A
B1_q[8]_data_in = data_in[8];
B1_q[8]_write_enable = sel;
B1_q[8]_clock_0 = !GLOBAL(ad_sts);
B1_q[8]_clock_1 = !GLOBAL(ad_sts);
B1_q[8]_clock_enable_1 = sel;
B1_q[8]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[8]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[8] = MEMORY_SEGMENT(B1_q[8]_data_in, B1_q[8]_write_enable, B1_q[8]_clock_0, B1_q[8]_clock_1, , , B1_q[8]_clock_enable_1, VCC, B1_q[8]_write_address, B1_q[8]_read_address);


--B1_q[9] is altdpram:mema_rtl_0|q[9] at EC13_A
B1_q[9]_data_in = data_in[9];
B1_q[9]_write_enable = sel;
B1_q[9]_clock_0 = !GLOBAL(ad_sts);
B1_q[9]_clock_1 = !GLOBAL(ad_sts);
B1_q[9]_clock_enable_1 = sel;
B1_q[9]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[9]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[9] = MEMORY_SEGMENT(B1_q[9]_data_in, B1_q[9]_write_enable, B1_q[9]_clock_0, B1_q[9]_clock_1, , , B1_q[9]_clock_enable_1, VCC, B1_q[9]_write_address, B1_q[9]_read_address);


--B1_q[10] is altdpram:mema_rtl_0|q[10] at EC1_A
B1_q[10]_data_in = data_in[10];
B1_q[10]_write_enable = sel;
B1_q[10]_clock_0 = !GLOBAL(ad_sts);
B1_q[10]_clock_1 = !GLOBAL(ad_sts);
B1_q[10]_clock_enable_1 = sel;
B1_q[10]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[10]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[10] = MEMORY_SEGMENT(B1_q[10]_data_in, B1_q[10]_write_enable, B1_q[10]_clock_0, B1_q[10]_clock_1, , , B1_q[10]_clock_enable_1, VCC, B1_q[10]_write_address, B1_q[10]_read_address);


--B1_q[11] is altdpram:mema_rtl_0|q[11] at EC12_A
B1_q[11]_data_in = data_in[11];
B1_q[11]_write_enable = sel;
B1_q[11]_clock_0 = !GLOBAL(ad_sts);
B1_q[11]_clock_1 = !GLOBAL(ad_sts);
B1_q[11]_clock_enable_1 = sel;
B1_q[11]_write_address = WR_ADDR(num[0], num[1], num[2], num[2], num[2], num[2], num[2], num[2]);
B1_q[11]_read_address = RD_ADDR(B1L71, A1L2, A1L3, A1L3, A1L3, A1L3, A1L3, A1L3);
B1_q[11] = MEMORY_SEGMENT(B1_q[11]_data_in, B1_q[11]_write_enable, B1_q[11]_clock_0, B1_q[11]_clock_1, , , B1_q[11]_clock_enable_1, VCC, B1_q[11]_write_address, B1_q[11]_read_address);


--num[0] is num[0] at LC5_A26
--operation mode is normal

num[0]_lut_out = !num[0];
num[0] = DFFEA(num[0]_lut_out, !GLOBAL(ad_sts), , , sel, , );

--A1L43Q is num[0]~6 at LC5_A26
--operation mode is normal

A1L43Q = num[0];


--num[1] is num[1] at LC7_A26
--operation mode is normal

num[1]_lut_out = num[1] $ num[0];
num[1] = DFFEA(num[1]_lut_out, !GLOBAL(ad_sts), , , sel, , );

--A1L63Q is num[1]~7 at LC7_A26
--operation mode is normal

A1L63Q = num[1];


--num[2] is num[2] at LC4_A26
--operation mode is normal

num[2]_lut_out = num[2] $ (num[1] & num[0]);
num[2] = DFFEA(num[2]_lut_out, !GLOBAL(ad_sts), , , sel, , );

--A1L83Q is num[2]~8 at LC4_A26
--operation mode is normal

A1L83Q = num[2];


--A1L2 is add~23 at LC3_A26
--operation mode is normal

A1L2 = num[1] $ num[0];

--A1L4 is add~27 at LC3_A26
--operation mode is normal

A1L4 = num[1] $ num[0];


--A1L3 is add~24 at LC1_A26
--operation mode is normal

A1L3 = num[2] $ (num[1] & num[0]);

--A1L5 is add~28 at LC1_A26
--operation mode is normal

A1L5 = num[2] $ (num[1] & num[0]);


--B1L71 is altdpram:mema_rtl_0|segment[0][0]~0 at LC2_A26
--operation mode is normal

B1L71 = !num[0];

--B1L81 is altdpram:mema_rtl_0|segment[0][0]~1 at LC2_A26
--operation mode is normal

B1L81 = !num[0];


--data_in[0] is data_in[0] at PIN_182
--operation mode is input

data_in[0] = INPUT();


--ad_sts is ad_sts at PIN_79
--operation mode is input

ad_sts = INPUT();


--data_in[1] is data_in[1] at PIN_78
--operation mode is input

data_in[1] = INPUT();


--data_in[2] is data_in[2] at PIN_80
--operation mode is input

data_in[2] = INPUT();


--data_in[3] is data_in[3] at PIN_183
--operation mode is input

data_in[3] = INPUT();


--data_in[4] is data_in[4] at PIN_7
--operation mode is input

data_in[4] = INPUT();


--data_in[5] is data_in[5] at PIN_85
--operation mode is input

data_in[5] = INPUT();


--data_in[6] is data_in[6] at PIN_159
--operation mode is input

data_in[6] = INPUT();


--data_in[7] is data_in[7] at PIN_99
--operation mode is input

data_in[7] = INPUT();


--data_in[8] is data_in[8] at PIN_94
--operation mode is input

data_in[8] = INPUT();


--data_in[9] is data_in[9] at PIN_102
--operation mode is input

data_in[9] = INPUT();


--data_in[10] is data_in[10] at PIN_170
--operation mode is input

data_in[10] = INPUT();


--data_in[11] is data_in[11] at PIN_95
--operation mode is input

data_in[11] = INPUT();


--sel is sel at PIN_184
--operation mode is input

sel = INPUT();


--data_out[0] is data_out[0] at PIN_37
--operation mode is output

data_out[0] = OUTPUT(B1_q[0]);


--data_out[1] is data_out[1] at PIN_148
--operation mode is output

data_out[1] = OUTPUT(B1_q[1]);


--data_out[2] is data_out[2] at PIN_9
--operation mode is output

data_out[2] = OUTPUT(B1_q[2]);


--data_out[3] is data_out[3] at PIN_149
--operation mode is output

data_out[3] = OUTPUT(B1_q[3]);


--data_out[4] is data_out[4] at PIN_8
--operation mode is output

data_out[4] = OUTPUT(B1_q[4]);


--data_out[5] is data_out[5] at PIN_143
--operation mode is output

data_out[5] = OUTPUT(B1_q[5]);


--data_out[6] is data_out[6] at PIN_14
--operation mode is output

data_out[6] = OUTPUT(B1_q[6]);


--data_out[7] is data_out[7] at PIN_10
--operation mode is output

data_out[7] = OUTPUT(B1_q[7]);


--data_out[8] is data_out[8] at PIN_45
--operation mode is output

data_out[8] = OUTPUT(B1_q[8]);


--data_out[9] is data_out[9] at PIN_150
--operation mode is output

data_out[9] = OUTPUT(B1_q[9]);


--data_out[10] is data_out[10] at PIN_24
--operation mode is output

data_out[10] = OUTPUT(B1_q[10]);


--data_out[11] is data_out[11] at PIN_16
--operation mode is output

data_out[11] = OUTPUT(B1_q[11]);