txd.map.summary

来自「用verilog实现的串口收发数据程序」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Wed Dec 05 15:58:46 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : txd
Top-level Entity Name : txd
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 16
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0