📄 txd.tan.rpt
字号:
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; n.0110 ; clk ; clk ; None ; None ; 2.476 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; txd~reg0 ; clk ; clk ; None ; None ; 2.476 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; n.0111 ; clk ; clk ; None ; None ; 2.313 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; n.1001 ; clk ; clk ; None ; None ; 2.313 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; n.0101 ; clk ; clk ; None ; None ; 2.313 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; n.0110 ; clk ; clk ; None ; None ; 2.313 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; txd~reg0 ; clk ; clk ; None ; None ; 2.313 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0000 ; clk ; clk ; None ; None ; 2.285 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0001 ; clk ; clk ; None ; None ; 2.285 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0010 ; clk ; clk ; None ; None ; 2.285 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0011 ; clk ; clk ; None ; None ; 2.285 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.1000 ; clk ; clk ; None ; None ; 2.285 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0100 ; clk ; clk ; None ; None ; 2.285 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; n.0111 ; clk ; clk ; None ; None ; 2.229 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; n.1001 ; clk ; clk ; None ; None ; 2.229 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; n.0101 ; clk ; clk ; None ; None ; 2.229 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; n.0110 ; clk ; clk ; None ; None ; 2.229 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; txd~reg0 ; clk ; clk ; None ; None ; 2.229 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0111 ; clk ; clk ; None ; None ; 2.035 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.1001 ; clk ; clk ; None ; None ; 2.035 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0101 ; clk ; clk ; None ; None ; 2.035 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; n.0110 ; clk ; clk ; None ; None ; 2.035 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; txd~reg0 ; clk ; clk ; None ; None ; 2.035 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[2] ; clk ; clk ; None ; None ; 1.326 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[3] ; num[3] ; clk ; clk ; None ; None ; 1.279 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.1001 ; txd~reg0 ; clk ; clk ; None ; None ; 1.272 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0101 ; txd~reg0 ; clk ; clk ; None ; None ; 1.146 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[3] ; clk ; clk ; None ; None ; 1.137 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[1] ; clk ; clk ; None ; None ; 1.077 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[3] ; clk ; clk ; None ; None ; 1.077 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[0] ; num[0] ; clk ; clk ; None ; None ; 1.071 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0110 ; txd~reg0 ; clk ; clk ; None ; None ; 1.053 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.1001 ; n.0000 ; clk ; clk ; None ; None ; 1.047 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[2] ; num[2] ; clk ; clk ; None ; None ; 1.047 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[2] ; clk ; clk ; None ; None ; 0.888 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[1] ; clk ; clk ; None ; None ; 0.887 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; num[1] ; num[3] ; clk ; clk ; None ; None ; 0.887 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0100 ; n.0101 ; clk ; clk ; None ; None ; 0.877 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.1000 ; n.1001 ; clk ; clk ; None ; None ; 0.876 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0111 ; n.1000 ; clk ; clk ; None ; None ; 0.874 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0101 ; n.0110 ; clk ; clk ; None ; None ; 0.862 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0000 ; n.0001 ; clk ; clk ; None ; None ; 0.824 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0110 ; n.0111 ; clk ; clk ; None ; None ; 0.690 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0011 ; n.0100 ; clk ; clk ; None ; None ; 0.659 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0001 ; n.0010 ; clk ; clk ; None ; None ; 0.657 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; n.0010 ; n.0011 ; clk ; clk ; None ; None ; 0.653 ns ;
+-------+------------------------------------------------+--------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A ; None ; 6.578 ns ; txd~reg0 ; txd ; clk ;
+-------+--------------+------------+----------+-----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Dec 05 15:58:57 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off txd -c txd --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "num[3]" and destination register "n.0000"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.726 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N1; Fanout = 2; REG Node = 'num[3]'
Info: 2: + IC(0.545 ns) + CELL(0.590 ns) = 1.135 ns; Loc. = LC_X10_Y2_N8; Fanout = 11; COMB Node = 'reduce_nor~19'
Info: 3: + IC(0.724 ns) + CELL(0.867 ns) = 2.726 ns; Loc. = LC_X9_Y2_N6; Fanout = 1; REG Node = 'n.0000'
Info: Total cell delay = 1.457 ns ( 53.45 % )
Info: Total interconnect delay = 1.269 ns ( 46.55 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.903 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X9_Y2_N6; Fanout = 1; REG Node = 'n.0000'
Info: Total cell delay = 2.180 ns ( 75.09 % )
Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: - Longest clock path from clock "clk" to source register is 2.903 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y2_N1; Fanout = 2; REG Node = 'num[3]'
Info: Total cell delay = 2.180 ns ( 75.09 % )
Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "txd" through register "txd~reg0" is 6.578 ns
Info: + Longest clock path from clock "clk" to source register is 2.903 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 15; CLK Node = 'clk'
Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y2_N5; Fanout = 1; REG Node = 'txd~reg0'
Info: Total cell delay = 2.180 ns ( 75.09 % )
Info: Total interconnect delay = 0.723 ns ( 24.91 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 3.451 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y2_N5; Fanout = 1; REG Node = 'txd~reg0'
Info: 2: + IC(1.343 ns) + CELL(2.108 ns) = 3.451 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'txd'
Info: Total cell delay = 2.108 ns ( 61.08 % )
Info: Total interconnect delay = 1.343 ns ( 38.92 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Wed Dec 05 15:58:57 2007
Info: Elapsed time: 00:00:00
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