did.tan.summary

来自「用verilog实现的串口收发数据程序」· SUMMARY 代码 · 共 37 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.446 ns
From           : CLK_OUT~reg0
To             : CLK_OUT
From Clock     : CLK
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 250.63 MHz ( period = 3.990 ns )
From           : num[3]
To             : num[5]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------