did.map.eqn

用verilog实现的串口收发数据程序

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--A1L3Q is CLK_OUT~reg0
--operation mode is normal

A1L3Q_lut_out = num[5] # !A1L4 & num[4] & num[3];
A1L3Q = DFFEAS(A1L3Q_lut_out, CLK, VCC, , , , , , );


--num[2] is num[2]
--operation mode is normal

num[2]_lut_out = A1L5 & (A1L32 # !num[0] # !num[1]);
num[2] = DFFEAS(num[2]_lut_out, CLK, VCC, , , , , , );


--num[1] is num[1]
--operation mode is normal

num[1]_lut_out = A1L7;
num[1] = DFFEAS(num[1]_lut_out, CLK, VCC, , , , , , );


--A1L4 is LessThan~83
--operation mode is normal

A1L4 = !num[2] & !num[1];


--num[4] is num[4]
--operation mode is normal

num[4]_lut_out = A1L9 & (A1L32 # !num[0] # !num[1]);
num[4] = DFFEAS(num[4]_lut_out, CLK, VCC, , , , , , );


--num[3] is num[3]
--operation mode is normal

num[3]_lut_out = A1L11;
num[3] = DFFEAS(num[3]_lut_out, CLK, VCC, , , , , , );


--num[5] is num[5]
--operation mode is normal

num[5]_lut_out = A1L31 & (A1L32 # !num[0] # !num[1]);
num[5] = DFFEAS(num[5]_lut_out, CLK, VCC, , , , , , );


--A1L5 is add~91
--operation mode is arithmetic

A1L5_carry_eqn = A1L8;
A1L5 = num[2] $ (!A1L5_carry_eqn);

--A1L6 is add~93
--operation mode is arithmetic

A1L6 = CARRY(num[2] & (!A1L8));


--A1L32 is reduce_nor~28
--operation mode is normal

A1L32 = num[2] # num[3] # !num[4] # !num[5];


--num[0] is num[0]
--operation mode is normal

num[0]_lut_out = A1L41;
num[0] = DFFEAS(num[0]_lut_out, CLK, VCC, , , , , , );


--A1L7 is add~96
--operation mode is arithmetic

A1L7_carry_eqn = A1L51;
A1L7 = num[1] $ (A1L7_carry_eqn);

--A1L8 is add~98
--operation mode is arithmetic

A1L8 = CARRY(!A1L51 # !num[1]);


--A1L9 is add~101
--operation mode is arithmetic

A1L9_carry_eqn = A1L21;
A1L9 = num[4] $ (!A1L9_carry_eqn);

--A1L01 is add~103
--operation mode is arithmetic

A1L01 = CARRY(num[4] & (!A1L21));


--A1L11 is add~106
--operation mode is arithmetic

A1L11_carry_eqn = A1L6;
A1L11 = num[3] $ (A1L11_carry_eqn);

--A1L21 is add~108
--operation mode is arithmetic

A1L21 = CARRY(!A1L6 # !num[3]);


--A1L31 is add~111
--operation mode is normal

A1L31_carry_eqn = A1L01;
A1L31 = num[5] $ (A1L31_carry_eqn);


--A1L41 is add~116
--operation mode is arithmetic

A1L41 = !num[0];

--A1L51 is add~118
--operation mode is arithmetic

A1L51 = CARRY(num[0]);


--CLK is CLK
--operation mode is input

CLK = INPUT();


--CLK_OUT is CLK_OUT
--operation mode is output

CLK_OUT = OUTPUT(A1L3Q);