did.v

来自「用verilog实现的串口收发数据程序」· Verilog 代码 · 共 24 行

module did(CLK,CLK_OUT);
input CLK;
output CLK_OUT;
reg CLK_OUT;
reg[5:0] num;
always@(posedge CLK)
begin
 if(num<6'B01_1010)
   begin
    num=num+6'b00_0001;
    CLK_OUT=1'b0;
   end
  else if(num==6'b11_0011)
   begin
     num=6'b00000;
     CLK_OUT=1'b1;
   end
  else
   begin
     num=6'b000001+num;
     CLK_OUT=1'b1;
   end
end
endmodule