sent.fit.qmsg

用verilog实现的串口收发数据程序

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.063 ns register register " "Info: Estimated most critical path is register to register delay of 4.063 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LAB_X22_Y9 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X22_Y9; Fanout = 13; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.237 ns) + CELL(0.590 ns) 1.827 ns sld_hub:sld_hub_inst\|hub_tdo~293 2 COMB LAB_X20_Y10 1 " "Info: 2: + IC(1.237 ns) + CELL(0.590 ns) = 1.827 ns; Loc. = LAB_X20_Y10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~293'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "1.827 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.310 ns) + CELL(0.114 ns) 3.251 ns sld_hub:sld_hub_inst\|hub_tdo~294 3 COMB LAB_X20_Y9 1 " "Info: 3: + IC(1.310 ns) + CELL(0.114 ns) = 3.251 ns; Loc. = LAB_X20_Y9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~294'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "1.424 ns" { sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.738 ns) 4.063 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LAB_X20_Y9 0 " "Info: 4: + IC(0.074 ns) + CELL(0.738 ns) = 4.063 ns; Loc. = LAB_X20_Y9; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "0.812 ns" { sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.442 ns 35.49 % " "Info: Total cell delay = 1.442 ns ( 35.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.621 ns 64.51 % " "Info: Total interconnect delay = 2.621 ns ( 64.51 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "4.063 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 5 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 5%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[7\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[7\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[7\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[5\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[4\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[1\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[6\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[6\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[6\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[3\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRSR\|Q\[2\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] } "NODE_NAME" } }  } 0}  } { { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "vcc VCC " "Info: Pin vcc has VCC driving its datain port" {  } { { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 104 416 592 120 "vcc" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "vcc" } } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { vcc } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { vcc } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 14 23:27:06 2007 " "Info: Processing ended: Fri Dec 14 23:27:06 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:26 " "Info: Elapsed time: 00:00:26" {  } {  } 0}  } {  } 0}