sent.fit.qmsg

用verilog实现的串口收发数据程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 14 23:26:41 2007 " "Info: Processing started: Fri Dec 14 23:26:41 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off sent -c sent " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off sent -c sent" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "sent EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"sent\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 7 " "Info: No exact pin location assignment(s) for 4 pins of 7 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_reserved_tdo } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_reserved_tms } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_reserved_tck } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_reserved_tdi } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 152 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN 152" {  } { { "sent.bdf" "" { Schematic "F:/复件 FPGA程序/sent/sent.bdf" { { 88 -32 136 104 "CLK" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" "" { Report "F:/复件 FPGA程序/sent/db/sent_cmp.qrpt" Compiler "sent" "UNKNOWN" "V1" "F:/复件 FPGA程序/sent/db/sent.quartus_db" { Floorplan "F:/复件 FPGA程序/sent/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/sent/sent.fld" "" { Floorplan "F:/复件 FPGA程序/sent/sent.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "did:inst\|CLK_OUT Global clock " "Info: Automatically promoted signal \"did:inst\|CLK_OUT\" to use Global clock" {  } { { "../did/did.v" "" { Text "F:/复件 FPGA程序/did/did.v" 3 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_signaltap:sent\|reset_all Global clock " "Info: Automatically promoted some destinations of signal \"sld_signaltap:sent\|reset_all\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:sent\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination \"sld_signaltap:sent\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset\" may be non-global or may not use global clock" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } }  } 0}  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } }  } 0}