rec.fit.qmsg

用verilog实现的串口收发数据程序

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.695 ns register register " "Info: Estimated most critical path is register to register delay of 3.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LAB_X14_Y10 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y10; Fanout = 17; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.831 ns) + CELL(0.590 ns) 1.421 ns sld_hub:sld_hub_inst\|hub_tdo~293 2 COMB LAB_X16_Y10 1 " "Info: 2: + IC(0.831 ns) + CELL(0.590 ns) = 1.421 ns; Loc. = LAB_X16_Y10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~293'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.421 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.348 ns) + CELL(0.114 ns) 2.883 ns sld_hub:sld_hub_inst\|hub_tdo~294 3 COMB LAB_X15_Y11 1 " "Info: 3: + IC(1.348 ns) + CELL(0.114 ns) = 2.883 ns; Loc. = LAB_X15_Y11; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~294'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.462 ns" { sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.738 ns) 3.695 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LAB_X15_Y11 0 " "Info: 4: + IC(0.074 ns) + CELL(0.738 ns) = 3.695 ns; Loc. = LAB_X15_Y11; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "0.812 ns" { sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.442 ns 39.03 % " "Info: Total cell delay = 1.442 ns ( 39.03 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.253 ns 60.97 % " "Info: Total interconnect delay = 2.253 ns ( 60.97 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "3.695 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 7 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 7%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:rec\|reset_all " "Info: Node sld_signaltap:rec\|reset_all uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\]" } } } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1128 -1 0 } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|post_trigger_count_enable " "Info: Port clear -- assigned as a global for destination node sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|post_trigger_count_enable -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_state_machine:sm1\|post_trigger_count_enable" } } } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1017 -1 0 } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[1\]" } } } } { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { sld_signaltap:rec|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[0\]" } } } } { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { sld_signaltap:rec|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\] -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:rec\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:ram_data_shift_out\|dffs\[2\]" } } } } { "lpm_shiftreg.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf" 54 7 0 } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { sld_signaltap:rec|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out|dffs[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:rec\|bypass_reg_out " "Info: Port clear -- assigned as a global for destination node sld_signaltap:rec\|bypass_reg_out -- routed using non-global resources" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|bypass_reg_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:rec\|bypass_reg_out" } } } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { sld_signaltap:rec|bypass_reg_out } "NODE_NAME" } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|reset_all } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:rec\|reset_all" } } } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { sld_signaltap:rec|reset_all } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: The following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "vcc VCC " "Info: Pin vcc has VCC driving its datain port" {  } { { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 104 656 832 120 "vcc" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "vcc" } } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { vcc } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { vcc } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "in_en VCC " "Info: Pin in_en has VCC driving its datain port" {  } { { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 88 656 832 104 "in_en" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "in_en" } } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { in_en } "NODE_NAME" } "" } } { "F:/复件 FPGA程序/rec/rec.fld" "" { Floorplan "F:/复件 FPGA程序/rec/rec.fld" "" "" { in_en } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 14 23:12:31 2007 " "Info: Processing ended: Fri Dec 14 23:12:31 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0}  } {  } 0}