rec.tan.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK data_out\[2\] test_rec:inst1\|data_out\[2\] 12.721 ns register " "Info: tco from clock \"CLK\" to destination pin \"data_out\[2\]\" through register \"test_rec:inst1\|data_out\[2\]\" is 12.721 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.399 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_152 263 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 263; CLK Node = 'CLK'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { CLK } "NODE_NAME" } "" } } { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 88 48 216 104 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns did:inst\|CLK_OUT 2 REG LC_X8_Y10_N6 22 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 22; REG Node = 'did:inst\|CLK_OUT'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.680 ns" { CLK did:inst|CLK_OUT } "NODE_NAME" } "" } } { "../did/did.v" "" { Text "F:/复件 FPGA程序/did/did.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.539 ns) + CELL(0.711 ns) 7.399 ns test_rec:inst1\|data_out\[2\] 3 REG LC_X12_Y14_N4 3 " "Info: 3: + IC(3.539 ns) + CELL(0.711 ns) = 7.399 ns; Loc. = LC_X12_Y14_N4; Fanout = 3; REG Node = 'test_rec:inst1\|data_out\[2\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "4.250 ns" { did:inst|CLK_OUT test_rec:inst1|data_out[2] } "NODE_NAME" } "" } } { "../test_rec/test_rec.v" "" { Text "F:/复件 FPGA程序/test_rec/test_rec.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.10 % " "Info: Total cell delay = 3.115 ns ( 42.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.284 ns 57.90 % " "Info: Total interconnect delay = 4.284 ns ( 57.90 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "7.399 ns" { CLK did:inst|CLK_OUT test_rec:inst1|data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { CLK CLK~out0 did:inst|CLK_OUT test_rec:inst1|data_out[2] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../test_rec/test_rec.v" "" { Text "F:/复件 FPGA程序/test_rec/test_rec.v" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.098 ns + Longest register pin " "Info: + Longest register to pin delay is 5.098 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns test_rec:inst1\|data_out\[2\] 1 REG LC_X12_Y14_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y14_N4; Fanout = 3; REG Node = 'test_rec:inst1\|data_out\[2\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { test_rec:inst1|data_out[2] } "NODE_NAME" } "" } } { "../test_rec/test_rec.v" "" { Text "F:/复件 FPGA程序/test_rec/test_rec.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.990 ns) + CELL(2.108 ns) 5.098 ns data_out\[2\] 2 PIN PIN_207 0 " "Info: 2: + IC(2.990 ns) + CELL(2.108 ns) = 5.098 ns; Loc. = PIN_207; Fanout = 0; PIN Node = 'data_out\[2\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.098 ns" { test_rec:inst1|data_out[2] data_out[2] } "NODE_NAME" } "" } } { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 41.35 % " "Info: Total cell delay = 2.108 ns ( 41.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.990 ns 58.65 % " "Info: Total interconnect delay = 2.990 ns ( 58.65 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.098 ns" { test_rec:inst1|data_out[2] data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.098 ns" { test_rec:inst1|data_out[2] data_out[2] } { 0.000ns 2.990ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "7.399 ns" { CLK did:inst|CLK_OUT test_rec:inst1|data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.399 ns" { CLK CLK~out0 did:inst|CLK_OUT test_rec:inst1|data_out[2] } { 0.000ns 0.000ns 0.745ns 3.539ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.098 ns" { test_rec:inst1|data_out[2] data_out[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.098 ns" { test_rec:inst1|data_out[2] data_out[2] } { 0.000ns 2.990ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_149 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 3.477 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.477 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.292 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 318 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 318; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\] 2 REG LC_X13_Y10_N5 4 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X13_Y10_N5; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1015 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 % " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1015 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.830 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y10_N1 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.352 ns) + CELL(0.478 ns) 1.830 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\] 2 REG LC_X13_Y10_N5 4 " "Info: 2: + IC(1.352 ns) + CELL(0.478 ns) = 1.830 ns; Loc. = LC_X13_Y10_N5; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.830 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1015 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 26.12 % " "Info: Total cell delay = 0.478 ns ( 26.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.352 ns 73.88 % " "Info: Total interconnect delay = 1.352 ns ( 73.88 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.830 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.830 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 1.352ns } { 0.000ns 0.478ns } } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.830 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.830 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 1.352ns } { 0.000ns 0.478ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 14 23:12:37 2007 " "Info: Processing ended: Fri Dec 14 23:12:37 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}