rec.tan.qmsg

用verilog实现的串口收发数据程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "did:inst\|CLK_OUT " "Info: Detected ripple clock \"did:inst\|CLK_OUT\" as buffer" {  } { { "../did/did.v" "" { Text "F:/复件 FPGA程序/did/did.v" 3 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "did:inst\|CLK_OUT" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|match_out register sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\] 115.45 MHz 8.662 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 115.45 MHz between source register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|match_out\" and destination register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\]\" (period= 8.662 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.350 ns + Longest register register " "Info: + Longest register to register delay is 8.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|match_out 1 REG LC_X16_Y14_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y14_N6; Fanout = 1; REG Node = 'sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|match_out'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } "NODE_NAME" } "" } } { "sld_mbpmg.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 289 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.563 ns) + CELL(0.442 ns) 3.005 ns sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~171 2 COMB LC_X15_Y8_N4 1 " "Info: 2: + IC(2.563 ns) + CELL(0.442 ns) = 3.005 ns; Loc. = LC_X15_Y8_N4; Fanout = 1; COMB Node = 'sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~171'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "3.005 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~171 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.405 ns) + CELL(0.442 ns) 3.852 ns sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~174 3 COMB LC_X15_Y8_N7 2 " "Info: 3: + IC(0.405 ns) + CELL(0.442 ns) = 3.852 ns; Loc. = LC_X15_Y8_N7; Fanout = 2; COMB Node = 'sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~174'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "0.847 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~171 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~174 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.699 ns) + CELL(0.590 ns) 6.141 ns sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~176 4 COMB LC_X20_Y9_N9 5 " "Info: 4: + IC(1.699 ns) + CELL(0.590 ns) = 6.141 ns; Loc. = LC_X20_Y9_N9; Fanout = 5; COMB Node = 'sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~176'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.289 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~174 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~176 } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 849 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.602 ns) + CELL(0.607 ns) 8.350 ns sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\] 5 REG LC_X14_Y9_N4 2 " "Info: 5: + IC(1.602 ns) + CELL(0.607 ns) = 8.350 ns; Loc. = LC_X14_Y9_N4; Fanout = 2; REG Node = 'sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.209 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~176 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1128 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns 24.92 % " "Info: Total cell delay = 2.081 ns ( 24.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.269 ns 75.08 % " "Info: Total interconnect delay = 6.269 ns ( 75.08 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "8.350 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~171 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~174 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~176 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.350 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~171 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~174 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~176 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } { 0.000ns 2.563ns 0.405ns 1.699ns 1.602ns } { 0.000ns 0.442ns 0.442ns 0.590ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.051 ns - Smallest " "Info: - Smallest clock skew is -0.051 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_152 263 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 263; CLK Node = 'CLK'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { CLK } "NODE_NAME" } "" } } { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 88 48 216 104 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\] 2 REG LC_X14_Y9_N4 2 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X14_Y9_N4; Fanout = 2; REG Node = 'sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out\[0\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.434 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1128 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.903 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_152 263 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 263; CLK Node = 'CLK'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { CLK } "NODE_NAME" } "" } } { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 88 48 216 104 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|match_out 2 REG LC_X16_Y14_N6 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X16_Y14_N6; Fanout = 1; REG Node = 'sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|match_out'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.485 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } "NODE_NAME" } "" } } { "sld_mbpmg.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 289 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.954 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.903 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.954 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_mbpmg.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_mbpmg.vhd" 289 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_ela_control.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1128 -1 0 } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "8.350 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~171 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~174 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~176 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.350 ns" { sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~171 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~174 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~176 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } { 0.000ns 2.563ns 0.405ns 1.699ns 1.602ns } { 0.000ns 0.442ns 0.442ns 0.590ns 0.607ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.903 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { CLK CLK~out0 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.954 ns" { CLK sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 sld_signaltap:rec|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|hub_tdo 103.28 MHz 9.682 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 103.28 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 9.682 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.580 ns + Longest register register " "Info: + Longest register to register delay is 4.580 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LC_X14_Y10_N5 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y10_N5; Fanout = 17; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.299 ns) + CELL(0.590 ns) 1.889 ns sld_hub:sld_hub_inst\|hub_tdo~293 2 COMB LC_X16_Y10_N1 1 " "Info: 2: + IC(1.299 ns) + CELL(0.590 ns) = 1.889 ns; Loc. = LC_X16_Y10_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~293'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.889 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.234 ns) + CELL(0.442 ns) 3.565 ns sld_hub:sld_hub_inst\|hub_tdo~294 3 COMB LC_X15_Y11_N5 1 " "Info: 3: + IC(1.234 ns) + CELL(0.442 ns) = 3.565 ns; Loc. = LC_X15_Y11_N5; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~294'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.676 ns" { sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.607 ns) 4.580 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X15_Y11_N0 0 " "Info: 4: + IC(0.408 ns) + CELL(0.607 ns) = 4.580 ns; Loc. = LC_X15_Y11_N0; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.015 ns" { sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.639 ns 35.79 % " "Info: Total cell delay = 1.639 ns ( 35.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.941 ns 64.21 % " "Info: Total interconnect delay = 2.941 ns ( 64.21 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "4.580 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.580 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.299ns 1.234ns 0.408ns } { 0.000ns 0.590ns 0.442ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.292 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 318 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 318; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X15_Y11_N0 0 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X15_Y11_N0; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 % " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.292 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.292 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N1 318 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N1; Fanout = 318; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.581 ns) + CELL(0.711 ns) 5.292 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 2 REG LC_X14_Y10_N5 17 " "Info: 2: + IC(4.581 ns) + CELL(0.711 ns) = 5.292 ns; Loc. = LC_X14_Y10_N5; Fanout = 17; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.44 % " "Info: Total cell delay = 0.711 ns ( 13.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.581 ns 86.56 % " "Info: Total interconnect delay = 4.581 ns ( 86.56 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } } { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "4.580 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.580 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~293 sld_hub:sld_hub_inst|hub_tdo~294 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.299ns 1.234ns 0.408ns } { 0.000ns 0.590ns 0.442ns 0.607ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.292 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 4.581ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:rec\|acq_trigger_in_reg\[8\] rxd CLK 6.351 ns register " "Info: tsu for register \"sld_signaltap:rec\|acq_trigger_in_reg\[8\]\" (data pin = \"rxd\", clock pin = \"CLK\") is 6.351 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.268 ns + Longest pin register " "Info: + Longest pin to register delay is 9.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rxd 1 PIN PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_93; Fanout = 5; PIN Node = 'rxd'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { rxd } "NODE_NAME" } "" } } { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 104 352 520 120 "rxd" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.678 ns) + CELL(0.115 ns) 9.268 ns sld_signaltap:rec\|acq_trigger_in_reg\[8\] 2 REG LC_X15_Y14_N8 3 " "Info: 2: + IC(7.678 ns) + CELL(0.115 ns) = 9.268 ns; Loc. = LC_X15_Y14_N8; Fanout = 3; REG Node = 'sld_signaltap:rec\|acq_trigger_in_reg\[8\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "7.793 ns" { rxd sld_signaltap:rec|acq_trigger_in_reg[8] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns 17.16 % " "Info: Total cell delay = 1.590 ns ( 17.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.678 ns 82.84 % " "Info: Total interconnect delay = 7.678 ns ( 82.84 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "9.268 ns" { rxd sld_signaltap:rec|acq_trigger_in_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.268 ns" { rxd rxd~out0 sld_signaltap:rec|acq_trigger_in_reg[8] } { 0.000ns 0.000ns 7.678ns } { 0.000ns 1.475ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_152 263 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 263; CLK Node = 'CLK'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "" { CLK } "NODE_NAME" } "" } } { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 88 48 216 104 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sld_signaltap:rec\|acq_trigger_in_reg\[8\] 2 REG LC_X15_Y14_N8 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X15_Y14_N8; Fanout = 3; REG Node = 'sld_signaltap:rec\|acq_trigger_in_reg\[8\]'" {  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "1.485 ns" { CLK sld_signaltap:rec|acq_trigger_in_reg[8] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.954 ns" { CLK sld_signaltap:rec|acq_trigger_in_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 sld_signaltap:rec|acq_trigger_in_reg[8] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "9.268 ns" { rxd sld_signaltap:rec|acq_trigger_in_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.268 ns" { rxd rxd~out0 sld_signaltap:rec|acq_trigger_in_reg[8] } { 0.000ns 0.000ns 7.678ns } { 0.000ns 1.475ns 0.115ns } } } { "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" "" { Report "F:/复件 FPGA程序/rec/db/rec_cmp.qrpt" Compiler "rec" "UNKNOWN" "V1" "F:/复件 FPGA程序/rec/db/rec.quartus_db" { Floorplan "F:/复件 FPGA程序/rec/" "" "2.954 ns" { CLK sld_signaltap:rec|acq_trigger_in_reg[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { CLK CLK~out0 sld_signaltap:rec|acq_trigger_in_reg[8] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}