rec.map.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9ie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9ie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9ie " "Info: Found entity 1: decode_9ie" {  } { { "db/decode_9ie.tdf" "" { Text "F:/复件 FPGA程序/rec/db/decode_9ie.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_dffex-DFFEX " "Info: Found design unit 1: sld_dffex-DFFEX" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_dffex " "Info: Found entity 1: sld_dffex" {  } { { "sld_dffex.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "test_rec:inst1\|in_en High " "Info: Power-up level of register \"test_rec:inst1\|in_en\" is not specified -- using power-up level of High to minimize register" {  } { { "../test_rec/test_rec.v" "" { Text "F:/复件 FPGA程序/test_rec/test_rec.v" 4 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "test_rec:inst1\|in_en data_in VCC " "Warning: Reduced register \"test_rec:inst1\|in_en\" with stuck data_in port to stuck value VCC" {  } { { "../test_rec/test_rec.v" "" { Text "F:/复件 FPGA程序/test_rec/test_rec.v" 4 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "9 " "Info: Ignored 9 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "9 " "Info: Ignored 9 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[10\] sld_signaltap:rec\|acq_trigger_in_reg\[10\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[10\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[10\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[10\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[10\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[0\] sld_signaltap:rec\|acq_trigger_in_reg\[0\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[0\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[0\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[0\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[0\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[1\] sld_signaltap:rec\|acq_trigger_in_reg\[1\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[1\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[1\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[1\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[1\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[2\] sld_signaltap:rec\|acq_trigger_in_reg\[2\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[2\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[2\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[2\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[2\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[3\] sld_signaltap:rec\|acq_trigger_in_reg\[3\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[3\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[3\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[3\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[3\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[4\] sld_signaltap:rec\|acq_trigger_in_reg\[4\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[4\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[4\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[4\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[4\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[5\] sld_signaltap:rec\|acq_trigger_in_reg\[5\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[5\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[5\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[5\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[5\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[6\] sld_signaltap:rec\|acq_trigger_in_reg\[6\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[6\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[6\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[6\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[6\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[7\] sld_signaltap:rec\|acq_trigger_in_reg\[7\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[7\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[7\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[7\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[7\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[9\] sld_signaltap:rec\|acq_trigger_in_reg\[9\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[9\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[9\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[9\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[9\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_reg\[8\] sld_signaltap:rec\|acq_trigger_in_reg\[8\] " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_reg\[8\]\" merged to single register \"sld_signaltap:rec\|acq_trigger_in_reg\[8\]\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 434 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[8\] sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1\|holdff " "Info: Duplicate register \"sld_signaltap:rec\|acq_data_in_pipe_reg\[1\]\[8\]\" merged to single register \"sld_signaltap:rec\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1\|holdff\"" {  } { { "sld_signaltap.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 436 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "vcc VCC " "Warning: Pin \"vcc\" stuck at VCC" {  } { { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 104 656 832 120 "vcc" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "in_en VCC " "Warning: Pin \"in_en\" stuck at VCC" {  } { { "rec.bdf" "" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 88 656 832 104 "in_en" "" } } } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "sld_hub.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "475 " "Info: Implemented 475 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "445 " "Info: Implemented 445 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "11 " "Info: Implemented 11 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 14 23:12:17 2007 " "Info: Processing ended: Fri Dec 14 23:12:17 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0}  } {  } 0}