rec.map.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_oo8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_oo8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_oo8 " "Info: Found entity 1: cntr_oo8" {  } { { "db/cntr_oo8.tdf" "" { Text "F:/复件 FPGA程序/rec/db/cntr_oo8.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_g29.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_g29.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_g29 " "Info: Found entity 1: cntr_g29" {  } { { "db/cntr_g29.tdf" "" { Text "F:/复件 FPGA程序/rec/db/cntr_g29.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 262 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/comptree.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/comptree.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 comptree " "Info: Found entity 1: comptree" {  } { { "comptree.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/comptree.tdf" 102 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpchain " "Info: Found entity 1: cmpchain" {  } { { "cmpchain.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 84 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_acquisition_buffer-rtl " "Info: Found design unit 1: sld_acquisition_buffer-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 73 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 308 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_acquisition_buffer " "Info: Found entity 1: sld_acquisition_buffer" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 271 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_5u9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_5u9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_5u9 " "Info: Found entity 1: cntr_5u9" {  } { { "db/cntr_5u9.tdf" "" { Text "F:/复件 FPGA程序/rec/db/cntr_5u9.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rh92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rh92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rh92 " "Info: Found entity 1: altsyncram_rh92" {  } { { "db/altsyncram_rh92.tdf" "" { Text "F:/复件 FPGA程序/rec/db/altsyncram_rh92.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_8v7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_8v7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_8v7 " "Info: Found entity 1: cntr_8v7" {  } { { "db/cntr_8v7.tdf" "" { Text "F:/复件 FPGA程序/rec/db/cntr_8v7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rn7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rn7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rn7 " "Info: Found entity 1: cntr_rn7" {  } { { "db/cntr_rn7.tdf" "" { Text "F:/复件 FPGA程序/rec/db/cntr_rn7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "d:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "rec " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"rec\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|CLK acq_clk " "Info: Source node \"\|rec\|CLK\" connects to port \"acq_clk\"" {  } { { "rec.bdf" "CLK" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 88 48 216 104 "CLK" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[0\] acq_trigger_in\[0\] " "Info: Source node \"\|rec\|data_out\[0\]\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "rec.bdf" "data_out\[0\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[0\] acq_data_in\[0\] " "Info: Source node \"\|rec\|data_out\[0\]\" connects to port \"acq_data_in\[0\]\"" {  } { { "rec.bdf" "data_out\[0\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[1\] acq_trigger_in\[1\] " "Info: Source node \"\|rec\|data_out\[1\]\" connects to port \"acq_trigger_in\[1\]\"" {  } { { "rec.bdf" "data_out\[1\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[1\] acq_data_in\[1\] " "Info: Source node \"\|rec\|data_out\[1\]\" connects to port \"acq_data_in\[1\]\"" {  } { { "rec.bdf" "data_out\[1\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[2\] acq_trigger_in\[2\] " "Info: Source node \"\|rec\|data_out\[2\]\" connects to port \"acq_trigger_in\[2\]\"" {  } { { "rec.bdf" "data_out\[2\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[2\] acq_data_in\[2\] " "Info: Source node \"\|rec\|data_out\[2\]\" connects to port \"acq_data_in\[2\]\"" {  } { { "rec.bdf" "data_out\[2\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[3\] acq_trigger_in\[3\] " "Info: Source node \"\|rec\|data_out\[3\]\" connects to port \"acq_trigger_in\[3\]\"" {  } { { "rec.bdf" "data_out\[3\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[3\] acq_data_in\[3\] " "Info: Source node \"\|rec\|data_out\[3\]\" connects to port \"acq_data_in\[3\]\"" {  } { { "rec.bdf" "data_out\[3\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[4\] acq_trigger_in\[4\] " "Info: Source node \"\|rec\|data_out\[4\]\" connects to port \"acq_trigger_in\[4\]\"" {  } { { "rec.bdf" "data_out\[4\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[4\] acq_data_in\[4\] " "Info: Source node \"\|rec\|data_out\[4\]\" connects to port \"acq_data_in\[4\]\"" {  } { { "rec.bdf" "data_out\[4\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[5\] acq_trigger_in\[5\] " "Info: Source node \"\|rec\|data_out\[5\]\" connects to port \"acq_trigger_in\[5\]\"" {  } { { "rec.bdf" "data_out\[5\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[5\] acq_data_in\[5\] " "Info: Source node \"\|rec\|data_out\[5\]\" connects to port \"acq_data_in\[5\]\"" {  } { { "rec.bdf" "data_out\[5\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[6\] acq_trigger_in\[6\] " "Info: Source node \"\|rec\|data_out\[6\]\" connects to port \"acq_trigger_in\[6\]\"" {  } { { "rec.bdf" "data_out\[6\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[6\] acq_data_in\[6\] " "Info: Source node \"\|rec\|data_out\[6\]\" connects to port \"acq_data_in\[6\]\"" {  } { { "rec.bdf" "data_out\[6\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[7\] acq_trigger_in\[7\] " "Info: Source node \"\|rec\|data_out\[7\]\" connects to port \"acq_trigger_in\[7\]\"" {  } { { "rec.bdf" "data_out\[7\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|data_out\[7\] acq_data_in\[7\] " "Info: Source node \"\|rec\|data_out\[7\]\" connects to port \"acq_data_in\[7\]\"" {  } { { "rec.bdf" "data_out\[7\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 136 656 832 152 "data_out\[7..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|rxd acq_trigger_in\[8\] " "Info: Source node \"\|rec\|rxd\" connects to port \"acq_trigger_in\[8\]\"" {  } { { "rec.bdf" "rxd" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 104 352 520 120 "rxd" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|rxd acq_data_in\[8\] " "Info: Source node \"\|rec\|rxd\" connects to port \"acq_data_in\[8\]\"" {  } { { "rec.bdf" "rxd" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 104 352 520 120 "rxd" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|state\[0\] acq_trigger_in\[9\] " "Info: Source node \"\|rec\|state\[0\]\" connects to port \"acq_trigger_in\[9\]\"" {  } { { "rec.bdf" "state\[0\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 120 656 832 136 "state\[1..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|state\[0\] acq_data_in\[9\] " "Info: Source node \"\|rec\|state\[0\]\" connects to port \"acq_data_in\[9\]\"" {  } { { "rec.bdf" "state\[0\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 120 656 832 136 "state\[1..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|state\[1\] acq_trigger_in\[10\] " "Info: Source node \"\|rec\|state\[1\]\" connects to port \"acq_trigger_in\[10\]\"" {  } { { "rec.bdf" "state\[1\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 120 656 832 136 "state\[1..0\]" "" } } } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|rec\|state\[1\] acq_data_in\[10\] " "Info: Source node \"\|rec\|state\[1\]\" connects to port \"acq_data_in\[10\]\"" {  } { { "rec.bdf" "state\[1\]" { Schematic "F:/复件 FPGA程序/rec/rec.bdf" { { 120 656 832 136 "state\[1..0\]" "" } } } }  } 0}  } {  } 0}