secondwatch.vo

用VERILOG实现的秒表 用VERILOG实现的秒表

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.0 Build 33 02/05/2007 SJ Full Version"

// DATE "06/14/2008 12:38:44"

// 
// Device: Altera EP1C6Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module secondwatch (
	clkin,
	reset_n,
	key,
	switch,
	led,
	seven,
	seven_sel,
	mem_addr,
	mem_data,
	sram_be,
	sram_rd,
	sram_wr,
	sram_sel,
	flash_oe,
	flash_we,
	flash_cs,
	lcd_data,
	lcd_cs1,
	lcd_cs2,
	lcd_di,
	lcd_e,
	lcd_reset,
	lcd_rw,
	ps2_clk,
	ps2_data,
	ps2_2_clk,
	ps2_2_data,
	rxd,
	txd,
	rxd_2,
	txd_2,
	motor_counter,
	motor_pwm,
	da_a0,
	da_a1,
	da_data,
	da_ldac_n,
	da_wr_n,
	ad_convst_n,
	ad_sclk,
	ad_din,
	ad_dout,
	ad_rfs,
	ad_tfs,
	usb_addr,
	usb_data,
	usb_int,
	usb_rdy,
	usb_rst_n,
	usb_cs_n,
	usb_rd_n,
	usb_wr_n);
input 	clkin;
input 	reset_n;
input 	[8:0] key;
input 	[0:3] switch;
output 	[0:7] led;
output 	[7:0] seven;
output 	[0:3] seven_sel;
output 	[20:0] mem_addr;
inout 	[15:0] mem_data;
output 	[1:0] sram_be;
output 	sram_rd;
output 	sram_wr;
output 	sram_sel;
output 	flash_oe;
output 	flash_we;
output 	flash_cs;
inout 	[7:0] lcd_data;
output 	lcd_cs1;
output 	lcd_cs2;
output 	lcd_di;
output 	lcd_e;
output 	lcd_reset;
output 	lcd_rw;
output 	ps2_clk;
output 	ps2_data;
output 	ps2_2_clk;
output 	ps2_2_data;
input 	rxd;
output 	txd;
input 	rxd_2;
output 	txd_2;
input 	motor_counter;
output 	motor_pwm;
output 	da_a0;
output 	da_a1;
output 	[7:0] da_data;
output 	da_ldac_n;
output 	da_wr_n;
output 	ad_convst_n;
output 	ad_sclk;
output 	ad_din;
input 	ad_dout;
output 	ad_rfs;
output 	ad_tfs;
output 	[7:0] usb_addr;
inout 	[15:0] usb_data;
input 	usb_int;
input 	usb_rdy;
output 	usb_rst_n;
output 	usb_cs_n;
output 	usb_rd_n;
output 	usb_wr_n;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("secondwatch_v.sdo");
// synopsys translate_on

wire \fenpin_inst|lpm_counter_component|auto_generated|modulus_trigger ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella0~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella1~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella1~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella2~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella2~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella3~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella3~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella4~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella4~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella5~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella6~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella6~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella7~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella7~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella11~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella11~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella8~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella8~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella9~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella9~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella10~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella12~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella12~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella13~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella13~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella14~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella14~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella15~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella16~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella16~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella17~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella17~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella18~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella18~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella19~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella19~COUTCOUT1 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|counter_cella20~COUT ;
wire \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~162 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~163 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~164 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~165 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~166 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~167 ;
wire \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~0 ;
wire \~GND ;
wire \clkin~combout ;
wire \reset_n~combout ;
wire \fpcount_sl|cout[0]~63 ;
wire \fpcount_sl|cout[0]~63COUT1 ;
wire \fpcount_sl|cout[1]~62 ;
wire \fpcount_sl|cout[1]~62COUT1 ;
wire \fpcount_sl|cout[2]~61 ;
wire \fpcount_sl|cout[2]~61COUT1 ;
wire \fpcount_sl|cout[3]~60 ;
wire \fpcount_sl|cout[3]~60COUT1 ;
wire \fpcount_sl|cout[4]~59 ;
wire \fpcount_sl|cout[5]~58 ;
wire \fpcount_sl|cout[5]~58COUT1 ;
wire \fpcount_sl|cout[6]~57 ;
wire \fpcount_sl|cout[6]~57COUT1 ;
wire \fpcount_sl|cp ;
wire \jscount_sl|count[0]~674 ;
wire \jscount_sl|count[0]~674COUT1 ;
wire \jscount_sl|count[1]~676 ;
wire \jscount_sl|count[1]~676COUT1 ;
wire \jscount_sl|count[2]~677 ;
wire \jscount_sl|count[2]~677COUT1 ;
wire \jscount_sl|count[0]~678 ;
wire [15:0] \jscount_sl|count ;
wire [7:0] \fpcount_sl|cout ;
wire [20:0] \fenpin_inst|lpm_counter_component|auto_generated|safe_q ;


// atom is at LC_X7_Y5_N5
cyclone_lcell \fenpin_inst|lpm_counter_component|auto_generated|cout_bit (
// Equation(s):
// \fenpin_inst|lpm_counter_component|auto_generated|modulus_trigger  = \fenpin_inst|lpm_counter_component|auto_generated|counter_cella20~COUT  # \fenpin_inst|lpm_counter_component|auto_generated|cmpr1_aeb_int~0