dac.tan.qmsg

VHDL語言實驗數字鍾功能,可手動調時,設定閙鍾等

{ "Info" "ITDB_TSU_RESULT" "lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\] KK CLK 12.300 ns register " "Info: tsu for register \"lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\]\" (data pin = \"KK\", clock pin = \"CLK\") is 12.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.100 ns + Longest pin register " "Info: + Longest pin to register delay is 14.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns KK 1 PIN PIN_98 12 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_98; Fanout = 12; PIN Node = 'KK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KK } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.300 ns) + CELL(1.400 ns) 11.600 ns DATA1\[4\]~47 2 COMB LC1_C15 1 " "Info: 2: + IC(5.300 ns) + CELL(1.400 ns) = 11.600 ns; Loc. = LC1_C15; Fanout = 1; COMB Node = 'DATA1\[4\]~47'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.700 ns" { KK DATA1[4]~47 } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.000 ns) 14.100 ns lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\] 3 REG LC7_C2 3 " "Info: 3: + IC(1.500 ns) + CELL(1.000 ns) = 14.100 ns; Loc. = LC7_C2; Fanout = 3; REG Node = 'lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { DATA1[4]~47 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.300 ns ( 51.77 % ) " "Info: Total cell delay = 7.300 ns ( 51.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.800 ns ( 48.23 % ) " "Info: Total interconnect delay = 6.800 ns ( 48.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.100 ns" { KK DATA1[4]~47 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.100 ns" { KK KK~out DATA1[4]~47 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 5.300ns 1.500ns } { 0.000ns 4.900ns 1.400ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 14; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC7_C2 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_C2; Fanout = 3; REG Node = 'lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.100 ns" { KK DATA1[4]~47 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.100 ns" { KK KK~out DATA1[4]~47 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 5.300ns 1.500ns } { 0.000ns 4.900ns 1.400ns 1.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DD\[1\] lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 23.300 ns register " "Info: tco from clock \"CLK\" to destination pin \"DD\[1\]\" through register \"lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" is 23.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.300 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 14; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns FSS 2 REG LC1_C1 11 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C1; Fanout = 11; REG Node = 'FSS'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK FSS } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 6.300 ns lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 3 REG LC1_E27 29 " "Info: 3: + IC(3.400 ns) + CELL(0.000 ns) = 6.300 ns; Loc. = LC1_E27; Fanout = 29; REG Node = 'lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.400 ns" { FSS lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 39.68 % ) " "Info: Total cell delay = 2.500 ns ( 39.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.800 ns ( 60.32 % ) " "Info: Total interconnect delay = 3.800 ns ( 60.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.300 ns" { CLK FSS lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.300 ns" { CLK CLK~out FSS lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.500 ns + Longest register pin " "Info: + Longest register to pin delay is 16.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC1_E27 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_E27; Fanout = 29; REG Node = 'lpm_counter:Q_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns Mux6~20 2 COMB LC3_E7 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC3_E7; Fanout = 1; COMB Node = 'Mux6~20'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux6~20 } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 5.800 ns Mux6~22 3 COMB LC1_E7 1 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.800 ns; Loc. = LC1_E7; Fanout = 1; COMB Node = 'Mux6~22'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux6~20 Mux6~22 } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.600 ns) 9.500 ns Mux6~24 4 COMB LC7_E27 1 " "Info: 4: + IC(2.100 ns) + CELL(1.600 ns) = 9.500 ns; Loc. = LC7_E27; Fanout = 1; COMB Node = 'Mux6~24'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { Mux6~22 Mux6~24 } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(6.300 ns) 16.500 ns DD\[1\] 5 PIN PIN_42 0 " "Info: 5: + IC(0.700 ns) + CELL(6.300 ns) = 16.500 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'DD\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { Mux6~24 DD[1] } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.200 ns ( 67.88 % ) " "Info: Total cell delay = 11.200 ns ( 67.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.300 ns ( 32.12 % ) " "Info: Total interconnect delay = 5.300 ns ( 32.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.500 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux6~20 Mux6~22 Mux6~24 DD[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "16.500 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux6~20 Mux6~22 Mux6~24 DD[1] } { 0.000ns 2.200ns 0.300ns 2.100ns 0.700ns } { 0.000ns 1.700ns 1.600ns 1.600ns 6.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.300 ns" { CLK FSS lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.300 ns" { CLK CLK~out FSS lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.400ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.500 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux6~20 Mux6~22 Mux6~24 DD[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "16.500 ns" { lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Mux6~20 Mux6~22 Mux6~24 DD[1] } { 0.000ns 2.200ns 0.300ns 2.100ns 0.700ns } { 0.000ns 1.700ns 1.600ns 1.600ns 6.300ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] DATA\[3\] CLK -6.600 ns register " "Info: th for register \"lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" (data pin = \"DATA\[3\]\", clock pin = \"CLK\") is -6.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_126 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 14; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC6_C2 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_C2; Fanout = 3; REG Node = 'lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns DATA\[3\] 1 PIN PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'DATA\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DATA[3] } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.600 ns) 9.000 ns DATA1\[3\]~41 2 COMB LC1_C2 1 " "Info: 2: + IC(2.500 ns) + CELL(1.600 ns) = 9.000 ns; Loc. = LC1_C2; Fanout = 1; COMB Node = 'DATA1\[3\]~41'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { DATA[3] DATA1[3]~41 } "NODE_NAME" } } { "DAC.vhd" "" { Text "D:/0511034406/shiyan14/DAC.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 10.300 ns lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 3 REG LC6_C2 3 " "Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 10.300 ns; Loc. = LC6_C2; Fanout = 3; REG Node = 'lpm_counter:COUNT12_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { DATA1[3]~41 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 72.82 % ) " "Info: Total cell delay = 7.500 ns ( 72.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 27.18 % ) " "Info: Total interconnect delay = 2.800 ns ( 27.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.300 ns" { DATA[3] DATA1[3]~41 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.300 ns" { DATA[3] DATA[3]~out DATA1[3]~41 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.300 ns" { DATA[3] DATA1[3]~41 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.300 ns" { DATA[3] DATA[3]~out DATA1[3]~41 lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 0.300ns } { 0.000ns 4.900ns 1.600ns 1.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}