dac.tan.summary

VHDL語言實驗數字鍾功能,可手動調時,設定閙鍾等

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 12.300 ns
From           : KK
To             : lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[0]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 23.300 ns
From           : lpm_counter:Q_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
To             : DD[1]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -6.600 ns
From           : DATA[3]
To             : lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 108.70 MHz ( period = 9.200 ns )
From           : lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[3]
To             : lpm_counter:COUNT12_rtl_1|alt_counter_f10ke:wysi_counter|q[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK1'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 200.00 MHz ( period = 5.000 ns )
From           : lpm_counter:DATA2_rtl_2|alt_counter_f10ke:wysi_counter|q[0]
To             : lpm_counter:DATA2_rtl_2|alt_counter_f10ke:wysi_counter|q[11]
From Clock     : CLK1
To Clock       : CLK1
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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