_primary.vhd

来自「这是分别用vhdl和verilog语言编写的源程序」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity sum is
    port(
        A               : in     vl_logic;
        Co              : out    vl_logic;
        B               : in     vl_logic;
        S               : out    vl_logic;
        Ci              : in     vl_logic
    );
end sum;