i2c.tan.qmsg

verilog语言在maxII系列芯片上实现iic功能

{ "Info" "ITDB_TSU_RESULT" "sda_buf sda clk 7.881 ns register " "Info: tsu for register \"sda_buf\" (data pin = \"sda\", clock pin = \"clk\") is 7.881 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.891 ns + Longest pin register " "Info: + Longest pin to register delay is 14.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_78 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_78; Fanout = 1; PIN Node = 'sda'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { sda } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sda~1 2 COMB IOC_X17_Y3_N2 4 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X17_Y3_N2; Fanout = 4; COMB Node = 'sda~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.132 ns" { sda sda~1 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.410 ns) + CELL(0.914 ns) 8.456 ns Select~18711 3 COMB LC_X11_Y6_N4 3 " "Info: 3: + IC(6.410 ns) + CELL(0.914 ns) = 8.456 ns; Loc. = LC_X11_Y6_N4; Fanout = 3; COMB Node = 'Select~18711'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.324 ns" { sda~1 Select~18711 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.797 ns) + CELL(0.511 ns) 9.764 ns Select~18721 4 COMB LC_X11_Y6_N8 1 " "Info: 4: + IC(0.797 ns) + CELL(0.511 ns) = 9.764 ns; Loc. = LC_X11_Y6_N8; Fanout = 1; COMB Node = 'Select~18721'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.308 ns" { Select~18711 Select~18721 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.703 ns) + CELL(0.914 ns) 11.381 ns Select~18723 5 COMB LC_X11_Y6_N2 1 " "Info: 5: + IC(0.703 ns) + CELL(0.914 ns) = 11.381 ns; Loc. = LC_X11_Y6_N2; Fanout = 1; COMB Node = 'Select~18723'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.617 ns" { Select~18721 Select~18723 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.210 ns) + CELL(0.511 ns) 13.102 ns Select~18724 6 COMB LC_X10_Y6_N9 1 " "Info: 6: + IC(1.210 ns) + CELL(0.511 ns) = 13.102 ns; Loc. = LC_X10_Y6_N9; Fanout = 1; COMB Node = 'Select~18724'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.721 ns" { Select~18723 Select~18724 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(1.061 ns) 14.891 ns sda_buf 7 REG LC_X10_Y6_N6 20 " "Info: 7: + IC(0.728 ns) + CELL(1.061 ns) = 14.891 ns; Loc. = LC_X10_Y6_N6; Fanout = 20; REG Node = 'sda_buf'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.789 ns" { Select~18724 sda_buf } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.043 ns ( 33.87 % ) " "Info: Total cell delay = 5.043 ns ( 33.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.848 ns ( 66.13 % ) " "Info: Total interconnect delay = 9.848 ns ( 66.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "14.891 ns" { sda sda~1 Select~18711 Select~18721 Select~18723 Select~18724 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "14.891 ns" { sda sda~1 Select~18711 Select~18721 Select~18723 Select~18724 sda_buf } { 0.000ns 0.000ns 6.410ns 0.797ns 0.703ns 1.210ns 0.728ns } { 0.000ns 1.132ns 0.914ns 0.511ns 0.914ns 0.511ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.343 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.293 ns) + CELL(0.918 ns) 7.343 ns sda_buf 2 REG LC_X10_Y6_N6 20 " "Info: 2: + IC(5.293 ns) + CELL(0.918 ns) = 7.343 ns; Loc. = LC_X10_Y6_N6; Fanout = 20; REG Node = 'sda_buf'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.211 ns" { clk sda_buf } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.92 % ) " "Info: Total cell delay = 2.050 ns ( 27.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.293 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.293 ns ( 72.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "14.891 ns" { sda sda~1 Select~18711 Select~18721 Select~18723 Select~18724 sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "14.891 ns" { sda sda~1 Select~18711 Select~18721 Select~18723 Select~18724 sda_buf } { 0.000ns 0.000ns 6.410ns 0.797ns 0.703ns 1.210ns 0.728ns } { 0.000ns 1.132ns 0.914ns 0.511ns 0.914ns 0.511ns 1.061ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk sda_buf } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout sda_buf } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[7\] en\[1\]~reg0 20.348 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[7\]\" through register \"en\[1\]~reg0\" is 20.348 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.343 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.293 ns) + CELL(0.918 ns) 7.343 ns en\[1\]~reg0 2 REG LC_X13_Y4_N3 8 " "Info: 2: + IC(5.293 ns) + CELL(0.918 ns) = 7.343 ns; Loc. = LC_X13_Y4_N3; Fanout = 8; REG Node = 'en\[1\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.211 ns" { clk en[1]~reg0 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 698 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.92 % ) " "Info: Total cell delay = 2.050 ns ( 27.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.293 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.293 ns ( 72.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk en[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout en[1]~reg0 } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 698 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.629 ns + Longest register pin " "Info: + Longest register to pin delay is 12.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[1\]~reg0 1 REG LC_X13_Y4_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y4_N3; Fanout = 8; REG Node = 'en\[1\]~reg0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { en[1]~reg0 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 698 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.956 ns) + CELL(0.914 ns) 3.870 ns seg_data_buf\[2\]~520 2 COMB LC_X12_Y8_N7 7 " "Info: 2: + IC(2.956 ns) + CELL(0.914 ns) = 3.870 ns; Loc. = LC_X12_Y8_N7; Fanout = 7; COMB Node = 'seg_data_buf\[2\]~520'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "3.870 ns" { en[1]~reg0 seg_data_buf[2]~520 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.010 ns) + CELL(0.740 ns) 6.620 ns reduce_or~2174 3 COMB LC_X12_Y10_N4 1 " "Info: 3: + IC(2.010 ns) + CELL(0.740 ns) = 6.620 ns; Loc. = LC_X12_Y10_N4; Fanout = 1; COMB Node = 'reduce_or~2174'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "2.750 ns" { seg_data_buf[2]~520 reduce_or~2174 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.777 ns) + CELL(0.511 ns) 7.908 ns reduce_or~2175 4 COMB LC_X12_Y10_N1 1 " "Info: 4: + IC(0.777 ns) + CELL(0.511 ns) = 7.908 ns; Loc. = LC_X12_Y10_N1; Fanout = 1; COMB Node = 'reduce_or~2175'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.288 ns" { reduce_or~2174 reduce_or~2175 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.399 ns) + CELL(2.322 ns) 12.629 ns seg_data\[7\] 5 PIN PIN_109 0 " "Info: 5: + IC(2.399 ns) + CELL(2.322 ns) = 12.629 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'seg_data\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "4.721 ns" { reduce_or~2175 seg_data[7] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.487 ns ( 35.53 % ) " "Info: Total cell delay = 4.487 ns ( 35.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.142 ns ( 64.47 % ) " "Info: Total interconnect delay = 8.142 ns ( 64.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "12.629 ns" { en[1]~reg0 seg_data_buf[2]~520 reduce_or~2174 reduce_or~2175 seg_data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.629 ns" { en[1]~reg0 seg_data_buf[2]~520 reduce_or~2174 reduce_or~2175 seg_data[7] } { 0.000ns 2.956ns 2.010ns 0.777ns 2.399ns } { 0.000ns 0.914ns 0.740ns 0.511ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk en[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout en[1]~reg0 } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "12.629 ns" { en[1]~reg0 seg_data_buf[2]~520 reduce_or~2174 reduce_or~2175 seg_data[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.629 ns" { en[1]~reg0 seg_data_buf[2]~520 reduce_or~2174 reduce_or~2175 seg_data[7] } { 0.000ns 2.956ns 2.010ns 0.777ns 2.399ns } { 0.000ns 0.914ns 0.740ns 0.511ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "writeData_reg\[2\] data_in\[2\] clk 1.154 ns register " "Info: th for register \"writeData_reg\[2\]\" (data pin = \"data_in\[2\]\", clock pin = \"clk\") is 1.154 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.343 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 79 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 79; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.293 ns) + CELL(0.918 ns) 7.343 ns writeData_reg\[2\] 2 REG LC_X12_Y6_N1 2 " "Info: 2: + IC(5.293 ns) + CELL(0.918 ns) = 7.343 ns; Loc. = LC_X12_Y6_N1; Fanout = 2; REG Node = 'writeData_reg\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.211 ns" { clk writeData_reg[2] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.92 % ) " "Info: Total cell delay = 2.050 ns ( 27.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.293 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.293 ns ( 72.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk writeData_reg[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout writeData_reg[2] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.410 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns data_in\[2\] 1 PIN PIN_68 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_68; Fanout = 1; PIN Node = 'data_in\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { data_in[2] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.687 ns) + CELL(0.591 ns) 6.410 ns writeData_reg\[2\] 2 REG LC_X12_Y6_N1 2 " "Info: 2: + IC(4.687 ns) + CELL(0.591 ns) = 6.410 ns; Loc. = LC_X12_Y6_N1; Fanout = 2; REG Node = 'writeData_reg\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "5.278 ns" { data_in[2] writeData_reg[2] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 26.88 % ) " "Info: Total cell delay = 1.723 ns ( 26.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.687 ns ( 73.12 % ) " "Info: Total interconnect delay = 4.687 ns ( 73.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.410 ns" { data_in[2] writeData_reg[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.410 ns" { data_in[2] data_in[2]~combout writeData_reg[2] } { 0.000ns 0.000ns 4.687ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "7.343 ns" { clk writeData_reg[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.343 ns" { clk clk~combout writeData_reg[2] } { 0.000ns 0.000ns 5.293ns } { 0.000ns 1.132ns 0.918ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "6.410 ns" { data_in[2] writeData_reg[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.410 ns" { data_in[2] data_in[2]~combout writeData_reg[2] } { 0.000ns 0.000ns 4.687ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0 0 "All timing requirements were met. See Report window for more details." 0 0}