i2c.fit.qmsg

verilog语言在maxII系列芯片上实现iic功能

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0 0 "Finished moving registers into LUTs" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[4\] " "Warning: Node \"data_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[4\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[5\] " "Warning: Node \"data_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[5\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[6\] " "Warning: Node \"data_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[6\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "data_in\[7\] " "Warning: Node \"data_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "data_in\[7\]" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.208 ns register register " "Info: Estimated most critical path is register to register delay of 9.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inner_state.start 1 REG LAB_X10_Y5 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y5; Fanout = 16; REG Node = 'inner_state.start'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { inner_state.start } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.914 ns) 1.360 ns readData_reg\[0\]~77 2 COMB LAB_X10_Y5 6 " "Info: 2: + IC(0.446 ns) + CELL(0.914 ns) = 1.360 ns; Loc. = LAB_X10_Y5; Fanout = 6; COMB Node = 'readData_reg\[0\]~77'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.360 ns" { inner_state.start readData_reg[0]~77 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.740 ns) 3.000 ns Select~18683 3 COMB LAB_X11_Y5 2 " "Info: 3: + IC(0.900 ns) + CELL(0.740 ns) = 3.000 ns; Loc. = LAB_X11_Y5; Fanout = 2; COMB Node = 'Select~18683'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.640 ns" { readData_reg[0]~77 Select~18683 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 4.183 ns Select~18685 4 COMB LAB_X11_Y5 2 " "Info: 4: + IC(0.672 ns) + CELL(0.511 ns) = 4.183 ns; Loc. = LAB_X11_Y5; Fanout = 2; COMB Node = 'Select~18685'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.183 ns" { Select~18683 Select~18685 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 5.366 ns Select~18786 5 COMB LAB_X11_Y5 1 " "Info: 5: + IC(0.672 ns) + CELL(0.511 ns) = 5.366 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Select~18786'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.183 ns" { Select~18685 Select~18786 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.983 ns) + CELL(0.200 ns) 6.549 ns Select~18686 6 COMB LAB_X11_Y5 1 " "Info: 6: + IC(0.983 ns) + CELL(0.200 ns) = 6.549 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Select~18686'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.183 ns" { Select~18786 Select~18686 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 7.732 ns Select~18687 7 COMB LAB_X11_Y5 1 " "Info: 7: + IC(0.672 ns) + CELL(0.511 ns) = 7.732 ns; Loc. = LAB_X11_Y5; Fanout = 1; COMB Node = 'Select~18687'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.183 ns" { Select~18686 Select~18687 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.804 ns) 9.208 ns inner_state.ack 8 REG LAB_X11_Y5 22 " "Info: 8: + IC(0.672 ns) + CELL(0.804 ns) = 9.208 ns; Loc. = LAB_X11_Y5; Fanout = 22; REG Node = 'inner_state.ack'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "1.476 ns" { Select~18687 inner_state.ack } "NODE_NAME" } "" } } { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.191 ns ( 45.51 % ) " "Info: Total cell delay = 4.191 ns ( 45.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.017 ns ( 54.49 % ) " "Info: Total interconnect delay = 5.017 ns ( 54.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "9.208 ns" { inner_state.start readData_reg[0]~77 Select~18683 Select~18685 Select~18786 Select~18686 Select~18687 inner_state.ack } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 7 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 7%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "link " "Info: Following pins have the same output enable: link" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sda LVTTL " "Info: Type bidirectional pin sda uses the LVTTL I/O standard" {  } { { "i2c.v" "" { Text "D:/My Docu/CPLD/i2c/i2c.v" 14 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "sda" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "i2c" "UNKNOWN" "V1" "D:/My Docu/CPLD/i2c/db/i2c.quartus_db" { Floorplan "D:/My Docu/CPLD/i2c/" "" "" { sda } "NODE_NAME" } "" } } { "D:/My Docu/CPLD/i2c/i2c.fld" "" { Floorplan "D:/My Docu/CPLD/i2c/i2c.fld" "" "" { sda } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 18 16:18:05 2007 " "Info: Processing ended: Sun Nov 18 16:18:05 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}