i2c.map.eqn

verilog语言在maxII系列芯片上实现iic功能

--clk_div[6] is clk_div[6]
--operation mode is normal

clk_div[6]_lut_out = A1L126 & (clk_div[3] # !A1L304 # !A1L303);
clk_div[6] = DFFEAS(clk_div[6]_lut_out, clk, rst, , , , , , );


--clk_div[4] is clk_div[4]
--operation mode is normal

clk_div[4]_lut_out = A1L128;
clk_div[4] = DFFEAS(clk_div[4]_lut_out, clk, rst, , , , , , );


--A1L304 is rtl~314
--operation mode is normal

A1L304 = cnt_scan[1] & clk_div[6] & (!clk_div[4]);


--clk_div[3] is clk_div[3]
--operation mode is normal

clk_div[3]_lut_out = A1L130;
clk_div[3] = DFFEAS(clk_div[3]_lut_out, clk, rst, , , , , , );


--A1L305 is rtl~315
--operation mode is normal

A1L305 = clk_div[4] & (!cnt_scan[1] & !clk_div[6]);


--A1L1 is Select~18654
--operation mode is normal

A1L1 = !wr_input # !rd_input;


--cnt_delay[17] is cnt_delay[17]
--operation mode is normal

cnt_delay[17]_lut_out = A1L132;
cnt_delay[17] = DFFEAS(cnt_delay[17]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[16] is cnt_delay[16]
--operation mode is normal

cnt_delay[16]_lut_out = A1L134;
cnt_delay[16] = DFFEAS(cnt_delay[16]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[15] is cnt_delay[15]
--operation mode is normal

cnt_delay[15]_lut_out = A1L136;
cnt_delay[15] = DFFEAS(cnt_delay[15]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[14] is cnt_delay[14]
--operation mode is normal

cnt_delay[14]_lut_out = A1L138;
cnt_delay[14] = DFFEAS(cnt_delay[14]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L306 is rtl~316
--operation mode is normal

A1L306 = !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14];


--cnt_delay[11] is cnt_delay[11]
--operation mode is normal

cnt_delay[11]_lut_out = A1L140;
cnt_delay[11] = DFFEAS(cnt_delay[11]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[9] is cnt_delay[9]
--operation mode is normal

cnt_delay[9]_lut_out = A1L142;
cnt_delay[9] = DFFEAS(cnt_delay[9]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[7] is cnt_delay[7]
--operation mode is normal

cnt_delay[7]_lut_out = A1L144;
cnt_delay[7] = DFFEAS(cnt_delay[7]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[6] is cnt_delay[6]
--operation mode is normal

cnt_delay[6]_lut_out = A1L146;
cnt_delay[6] = DFFEAS(cnt_delay[6]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L307 is rtl~317
--operation mode is normal

A1L307 = !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6];


--cnt_delay[5] is cnt_delay[5]
--operation mode is normal

cnt_delay[5]_lut_out = A1L148;
cnt_delay[5] = DFFEAS(cnt_delay[5]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[4] is cnt_delay[4]
--operation mode is normal

cnt_delay[4]_lut_out = A1L150;
cnt_delay[4] = DFFEAS(cnt_delay[4]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[3] is cnt_delay[3]
--operation mode is normal

cnt_delay[3]_lut_out = A1L152;
cnt_delay[3] = DFFEAS(cnt_delay[3]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[2] is cnt_delay[2]
--operation mode is normal

cnt_delay[2]_lut_out = A1L154;
cnt_delay[2] = DFFEAS(cnt_delay[2]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L308 is rtl~318
--operation mode is normal

A1L308 = !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2];


--cnt_delay[1] is cnt_delay[1]
--operation mode is normal

cnt_delay[1]_lut_out = A1L156;
cnt_delay[1] = DFFEAS(cnt_delay[1]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[0] is cnt_delay[0]
--operation mode is normal

cnt_delay[0]_lut_out = A1L158 & (!A1L312 # !A1L310);
cnt_delay[0] = DFFEAS(cnt_delay[0]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L309 is rtl~319
--operation mode is normal

A1L309 = !cnt_delay[1] & !cnt_delay[0];


--A1L310 is rtl~320
--operation mode is normal

A1L310 = A1L306 & A1L307 & A1L308 & A1L309;


--cnt_delay[19] is cnt_delay[19]
--operation mode is normal

cnt_delay[19]_lut_out = A1L160 & (!A1L312 # !A1L310);
cnt_delay[19] = DFFEAS(cnt_delay[19]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[18] is cnt_delay[18]
--operation mode is normal

cnt_delay[18]_lut_out = A1L161 & (!A1L312 # !A1L310);
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[13] is cnt_delay[13]
--operation mode is normal

cnt_delay[13]_lut_out = A1L163 & (!A1L312 # !A1L310);
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[12] is cnt_delay[12]
--operation mode is normal

cnt_delay[12]_lut_out = A1L165 & (!A1L312 # !A1L310);
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L311 is rtl~321
--operation mode is normal

A1L311 = cnt_delay[19] & cnt_delay[18] & cnt_delay[13] & cnt_delay[12];


--cnt_delay[10] is cnt_delay[10]
--operation mode is normal

cnt_delay[10]_lut_out = A1L167 & (!A1L312 # !A1L310);
cnt_delay[10] = DFFEAS(cnt_delay[10]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[8] is cnt_delay[8]
--operation mode is normal

cnt_delay[8]_lut_out = A1L169 & (!A1L312 # !A1L310);
cnt_delay[8] = DFFEAS(cnt_delay[8]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L312 is rtl~322
--operation mode is normal

A1L312 = A1L311 & cnt_delay[10] & cnt_delay[8];


--A1L2 is Select~18655
--operation mode is normal

A1L2 = !main_state.00 & (!A1L312 # !A1L310 # !A1L1);


--main_state.01 is main_state.01
--operation mode is normal

main_state.01_lut_out = !A1L110 & (A1L11 & (!wr_input) # !A1L11 & A1L34);
main_state.01 = DFFEAS(main_state.01_lut_out, clk, rst, , , , , , );


--i2c_state.read_ini is i2c_state.read_ini
--operation mode is normal

i2c_state.read_ini_lut_out = main_state.10 & (A1L18 # i2c_state.read_ini & A1L35) # !main_state.10 & i2c_state.read_ini & A1L35;
i2c_state.read_ini = DFFEAS(i2c_state.read_ini_lut_out, clk, rst, , , , , , );


--A1L279 is reduce_nor~75
--operation mode is normal

A1L279 = i2c_state.read_data # i2c_state.read_ini;


--i2c_state.sendaddr is i2c_state.sendaddr
--operation mode is normal

i2c_state.sendaddr_lut_out = A1L36 # main_state.10 & i2c_state.sendaddr & !A1L16;
i2c_state.sendaddr = DFFEAS(i2c_state.sendaddr_lut_out, clk, rst, , , , , , );


--i2c_state.ini is i2c_state.ini
--operation mode is normal

i2c_state.ini_lut_out = main_state.10 & (i2c_state.ini # !A1L37) # !main_state.10 & main_state.01 & (i2c_state.ini # !A1L37);
i2c_state.ini = DFFEAS(i2c_state.ini_lut_out, clk, rst, , , , , , );


--A1L3 is Select~18656
--operation mode is normal

A1L3 = inner_state.ack & (i2c_state.read_ini # i2c_state.sendaddr # !i2c_state.ini);


--A1L4 is Select~18657
--operation mode is normal

A1L4 = A1L120 & (A1L269 & inner_state.stop # !A1L269 & (phase1));


--i2c_state.write_data is i2c_state.write_data
--operation mode is normal

i2c_state.write_data_lut_out = main_state.01 & (i2c_state.write_data # A1L18) # !main_state.01 & i2c_state.write_data & main_state.10;
i2c_state.write_data = DFFEAS(i2c_state.write_data_lut_out, clk, rst, , , , , , );


--A1L5 is Select~18658
--operation mode is normal

A1L5 = main_state.01 & (A1L279 # i2c_state.write_data & !inner_state.ack);


--A1L6 is Select~18659
--operation mode is normal

A1L6 = A1L4 # inner_state.stop & A1L5 & !A1L279;


--phase3 is phase3
--operation mode is normal

phase3_lut_out = phase3 # A1L298;
phase3 = DFFEAS(phase3_lut_out, clk, rst, , , , , phase3, );


--A1L7 is Select~18660
--operation mode is normal

A1L7 = main_state.10 & (!i2c_state.read_data) # !main_state.10 & (!i2c_state.write_data # !inner_state.stop);


--sda_buf is sda_buf
--operation mode is normal

sda_buf_lut_out = !A1L65 & !A1L46 & !A1L71 # !A1L61;
sda_buf = DFFEAS(sda_buf_lut_out, clk, rst, , , , , , );


--A1L8 is Select~18661
--operation mode is normal

A1L8 = main_state.00 & (A1L7 & (!sda_buf) # !A1L7 & phase3);


--A1L313 is rtl~323
--operation mode is normal

A1L313 = !cnt_scan[0] & !clk_div[7] & !clk_div[2] & !clk_div[5];


--A1L297 is rtl~3
--operation mode is normal

A1L297 = clk_div[3] & A1L305 & A1L313;


--A1L9 is Select~18663
--operation mode is normal

A1L9 = !inner_state.stop # !phase3;


--A1L10 is Select~18664
--operation mode is normal

A1L10 = i2c_state.read_data & A1L9 # !i2c_state.read_data & (sda_buf # !phase1);


--A1L11 is Select~18665
--operation mode is normal

A1L11 = A1L1 & A1L310 & A1L312 & !main_state.00;


--A1L244 is i2c_state~122
--operation mode is normal

A1L244 = phase3 & inner_state.ack;


--A1L12 is Select~18667
--operation mode is normal

A1L12 = main_state.10 & i2c_state.read_ini;


--A1L13 is Select~18668
--operation mode is normal

A1L13 = main_state.10 # main_state.01;


--link is link
--operation mode is normal

link_lut_out = A1L81 # A1L82 # A1L30 & A1L84;
link = DFFEAS(link_lut_out, clk, rst, , , , , , );


--A1L173 is always2~2
--operation mode is normal

A1L173 = phase3 & link;


--A1L14 is Select~18670
--operation mode is normal

A1L14 = !inner_state.start & (i2c_state.ini # !A1L173) # !main_state.01;


--A1L15 is Select~18671
--operation mode is normal

A1L15 = i2c_state.read_ini & (!link # !phase3) # !i2c_state.read_ini & !i2c_state.ini & (!link # !phase3);


--A1L16 is Select~18672
--operation mode is normal

A1L16 = !i2c_state.read_data & !i2c_state.write_data;


--A1L17 is Select~18673
--operation mode is normal

A1L17 = !inner_state.start & (i2c_state.sendaddr # A1L15 # !A1L16);


--A1L18 is Select~18674
--operation mode is normal

A1L18 = phase3 & inner_state.ack & i2c_state.sendaddr;


--A1L19 is Select~18676
--operation mode is normal

A1L19 = A1L269 # main_state.01 & i2c_state.write_data & !phase1;


--inner_state.eighth is inner_state.eighth
--operation mode is normal

inner_state.eighth_lut_out = A1L86 # A1L87 # inner_state.eighth & A1L90;
inner_state.eighth = DFFEAS(inner_state.eighth_lut_out, clk, rst, , , , , , );


--A1L20 is Select~18678
--operation mode is normal

A1L20 = i2c_state.read_data # i2c_state.sendaddr;


--A1L21 is Select~18679
--operation mode is normal

A1L21 = A1L112 & inner_state.eighth # !A1L112 & (inner_state.ack);


--A1L22 is Select~18680
--operation mode is normal

A1L22 = main_state.10 & (i2c_state.write_data & inner_state.ack # !i2c_state.write_data & (A1L21));


--A1L23 is Select~18681
--operation mode is normal

A1L23 = i2c_state.write_data & inner_state.eighth;


--A1L24 is Select~18682
--operation mode is normal

A1L24 = main_state.01 & A1L23 & (phase3 # inner_state.ack);


--A1L25 is Select~18683
--operation mode is normal

A1L25 = inner_state.eighth # A1L270 & (!inner_state.ack # !phase1);


--A1L26 is Select~18684
--operation mode is normal

A1L26 = i2c_state.write_data & (A1L25 # !i2c_state.ini & !i2c_state.sendaddr) # !i2c_state.write_data & (!i2c_state.ini & !i2c_state.sendaddr);


--A1L27 is Select~18685
--operation mode is normal

A1L27 = i2c_state.sendaddr # i2c_state.write_data & A1L25;


--A1L28 is Select~18686
--operation mode is normal

A1L28 = A1L26 & (inner_state.ack $ (inner_state.eighth & !A1L113)) # !A1L26 & A1L113 & (inner_state.eighth $ inner_state.ack);


--A1L29 is Select~18687
--operation mode is normal

A1L29 = inner_state.ack $ (phase3 & A1L28);


--A1L30 is Select~18688
--operation mode is normal

A1L30 = main_state.01 & (!inner_state.eighth # !i2c_state.write_data);


--A1L121 is add~545
--operation mode is arithmetic

A1L121_carry_eqn = A1L129;
A1L121 = clk_div[5] $ (!A1L121_carry_eqn);

--A1L122 is add~547
--operation mode is arithmetic

A1L122 = CARRY(clk_div[5] & (!A1L129));


--A1L123 is add~550
--operation mode is normal

A1L123_carry_eqn = A1L127;
A1L123 = clk_div[7] $ (!A1L123_carry_eqn);


--A1L124 is add~555
--operation mode is arithmetic

A1L124_carry_eqn = A1L172;
A1L124 = clk_div[2] $ (A1L124_carry_eqn);

--A1L125 is add~557
--operation mode is arithmetic

A1L125 = CARRY(!A1L172 # !clk_div[2]);


--A1L126 is add~560