test.vhd

来自「实验四 频率计 实验要求：设计一个有效位为4位的十进制的数字频率计。」· VHDL 代码 · 共 62 行

Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Unsigned.All;
Entity test is     
	port(clk:in std_Logic;
	 horizontal,vertical: in std_logic_vector(3 downto 0);   
         out: out std_logic_vector(3 downto 0));
end entity;

architecture testbody Of test is
begin

process(clk)
begin

if rising_edge(clk) then
case horizontal is
     when "0111" =>
          case vertcal is
               when "0111" =>out<="0000";
               when "1011" =>out<="0001";
               when "1101" =>out<="0010";
               when "1110" =>out<="0011";
               when others => NULL;
          end case;
case horizontal is
     when "1011" =>
          case vertcal is
               when "0111" =>out<="0100";
               when "1011" =>out<="0101";
               when "1101" =>out<="0110";
               when "1110" =>out<="0111";
               when others => NULL;
          end case;
case horizontal is
     when "1101" =>
          case vertcal is
               when "0111" =>out<="1000";
               when "1011" =>out<="1001";
               when "1101" =>out<="1010";
               when "1110" =>out<="1011";
               when others => NULL;
          end case;   
case horizontal is
     when "1110" =>
          case vertcal is
               when "0111" =>out<="1100";
               when "1011" =>out<="1101";
               when "1101" =>out<="1110";
               when "1110" =>out<="1111";
               when others => NULL;
          end case;  
     when others => NULL;
end case; 

end if;
end process;


end testbody;