sin_gnt.tan.rpt

宏模块应用实例- 正弦信号发生器的实现

; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra1 ; DOUT[7] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra2 ; DOUT[7] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra3 ; DOUT[7] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra4 ; DOUT[7] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra5 ; DOUT[7] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra0 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra1 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra2 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra3 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra4 ; DOUT[3] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra5 ; DOUT[3] ; CLK        ;
+-------+--------------+------------+------------------------------------------------------------------------------------------------------------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Jun 03 11:50:01 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sin_gnt -c sin_gnt
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 200.0 MHz between source register "lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]" and destination memory "data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra5"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to memory delay is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C26; Fanout = 9; REG Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
            Info: 2: + IC(1.300 ns) + CELL(0.200 ns) = 1.500 ns; Loc. = EC9_C; Fanout = 1; MEM Node = 'data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra5'
            Info: Total cell delay = 0.200 ns ( 13.33 % )
            Info: Total interconnect delay = 1.300 ns ( 86.67 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination memory is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 67; CLK Node = 'CLK'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = EC9_C; Fanout = 1; MEM Node = 'data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra5'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
            Info: - Longest clock path from clock "CLK" to source register is 1.900 ns
                Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 67; CLK Node = 'CLK'
                Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC6_C26; Fanout = 9; REG Node = 'lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
                Info: Total cell delay = 0.500 ns ( 26.32 % )
                Info: Total interconnect delay = 1.400 ns ( 73.68 % )
        Info: + Micro clock to output delay of source is 1.100 ns
        Info: + Micro setup delay of destination is 1.400 ns
Info: tco from clock "CLK" to destination pin "DOUT[1]" through memory "data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra0" is 25.700 ns
    Info: + Longest clock path from clock "CLK" to source memory is 1.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 67; CLK Node = 'CLK'
        Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = EC11_C; Fanout = 1; MEM Node = 'data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra0'
        Info: Total cell delay = 0.500 ns ( 26.32 % )
        Info: Total interconnect delay = 1.400 ns ( 73.68 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest memory to pin delay is 23.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC11_C; Fanout = 1; MEM Node = 'data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra0'
        Info: 2: + IC(0.000 ns) + CELL(6.600 ns) = 6.600 ns; Loc. = EC11_C; Fanout = 1; MEM Node = 'data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~mem_cell_ra0'
        Info: 3: + IC(0.000 ns) + CELL(0.500 ns) = 7.100 ns; Loc. = EC11_C; Fanout = 1; MEM Node = 'data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]'
        Info: 4: + IC(5.000 ns) + CELL(1.700 ns) = 13.800 ns; Loc. = LC3_L29; Fanout = 1; COMB Node = 'DOUT[1]~1'
        Info: 5: + IC(0.900 ns) + CELL(8.600 ns) = 23.300 ns; Loc. = PIN_45; Fanout = 0; PIN Node = 'DOUT[1]'
        Info: Total cell delay = 17.400 ns ( 74.68 % )
        Info: Total interconnect delay = 5.900 ns ( 25.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jun 03 11:50:03 2008
    Info: Elapsed time: 00:00:02