sin_gnt.tan.rpt

来自「宏模块应用实例- 正弦信号发生器的实现」· RPT 代码 · 共 268 行 · 第 1/4 页

; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.900 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.700 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.700 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.300 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]                                                               ; CLK        ; CLK      ; None                        ; None                      ; 1.100 ns                ;
+-------+------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                               ;
+-------+--------------+------------+------------------------------------------------------------------------------------------------------------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                                                                   ; To      ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------------------------------------------------------------------+---------+------------+
; N/A   ; None         ; 25.700 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra0 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 25.700 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra1 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 25.700 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra2 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 25.700 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra3 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 25.700 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra4 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 25.700 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra5 ; DOUT[1] ; CLK        ;
; N/A   ; None         ; 24.600 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra0 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 24.600 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra1 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 24.600 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra2 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 24.600 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra3 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 24.600 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra4 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 24.600 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra5 ; DOUT[0] ; CLK        ;
; N/A   ; None         ; 24.500 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra0 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 24.500 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra1 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 24.500 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra2 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 24.500 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra3 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 24.500 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra4 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 24.500 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra5 ; DOUT[6] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra0 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra1 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra2 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra3 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra4 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra5 ; DOUT[4] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra0 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra1 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra2 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra3 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra4 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 24.200 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra5 ; DOUT[2] ; CLK        ;
; N/A   ; None         ; 24.000 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra0 ; DOUT[5] ; CLK        ;
; N/A   ; None         ; 24.000 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra1 ; DOUT[5] ; CLK        ;
; N/A   ; None         ; 24.000 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra2 ; DOUT[5] ; CLK        ;
; N/A   ; None         ; 24.000 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra3 ; DOUT[5] ; CLK        ;
; N/A   ; None         ; 24.000 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra4 ; DOUT[5] ; CLK        ;
; N/A   ; None         ; 24.000 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra5 ; DOUT[5] ; CLK        ;
; N/A   ; None         ; 23.800 ns  ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra0 ; DOUT[7] ; CLK        ;