sin_gnt.tan.rpt

宏模块应用实例- 正弦信号发生器的实现

; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                     ;
+-------+------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                     ; To                                                                                                                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.500 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]~reg_ra0 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra5 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra4 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra3 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra2 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]~reg_ra1 ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;