ls138.vhd

来自「基于VHDL的LS138译码器的实现 一个很简单的程序」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
entity ls138 is
  port( 
        en1 :in std_logic;
        en2a:in std_logic;
        en2b:in std_logic;
        a   :in std_logic;
        b   :in std_logic;
        c   :in std_logic;
        led8s:out std_logic_vector(7 downto 0));
end ls138;
architecture one of ls138 is
  signal ctrl: std_logic_vector(2 downto 0);
  signal din : std_logic_vector(2 downto 0);
begin
  ctrl <= en1 & en2a & en2b;
  din  <= c & b & a;
 process(ctrl,din)
 begin 
  if ctrl="100" then
    case din is
     when "000" => led8s <="01111111";
     when "001" => led8s <="10111111";
     when "010" => led8s <="11011111";
     when "011" => led8s <="11101111";
     when "100" => led8s <="11110111";
     when "101" => led8s <="11111011";
     when "110" => led8s <="11111101";
     when "111" => led8s <="11111110";
     when others => null;
    end case;
  else 
     led8s <="11111111";
  end if;
 end process;
end one;