myfirstproject.tan.qmsg

用VHDL原理图输入的方法实现d触发器的功能

{ "Info" "ITDB_TSU_RESULT" "D-flop DIn ClkIn 3.880 ns register " "Info: tsu for register \"D-flop\" (data pin = \"DIn\", clock pin = \"ClkIn\") is 3.880 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.839 ns + Longest pin register " "Info: + Longest pin to register delay is 6.839 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DIn 1 PIN PIN_58 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_58; Fanout = 1; PIN Node = 'DIn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DIn } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 144 88 256 160 "DIn" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.061 ns) + CELL(0.309 ns) 6.839 ns D-flop 2 REG LC_X1_Y4_N2 1 " "Info: 2: + IC(5.061 ns) + CELL(0.309 ns) = 6.839 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; REG Node = 'D-flop'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.370 ns" { DIn D-flop } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 26.00 % ) " "Info: Total cell delay = 1.778 ns ( 26.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.061 ns ( 74.00 % ) " "Info: Total interconnect delay = 5.061 ns ( 74.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.839 ns" { DIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.839 ns" { DIn DIn~out0 D-flop } { 0.000ns 0.000ns 5.061ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn destination 2.996 ns - Shortest register " "Info: - Shortest clock path from clock \"ClkIn\" to destination register is 2.996 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ClkIn 1 CLK PIN_48 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 1; CLK Node = 'ClkIn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 160 88 256 176 "ClkIn" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.711 ns) 2.996 ns D-flop 2 REG LC_X1_Y4_N2 1 " "Info: 2: + IC(0.816 ns) + CELL(0.711 ns) = 2.996 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; REG Node = 'D-flop'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.527 ns" { ClkIn D-flop } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.76 % ) " "Info: Total cell delay = 2.180 ns ( 72.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.816 ns ( 27.24 % ) " "Info: Total interconnect delay = 0.816 ns ( 27.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.996 ns" { ClkIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.996 ns" { ClkIn ClkIn~out0 D-flop } { 0.000ns 0.000ns 0.816ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.839 ns" { DIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.839 ns" { DIn DIn~out0 D-flop } { 0.000ns 0.000ns 5.061ns } { 0.000ns 1.469ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.996 ns" { ClkIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.996 ns" { ClkIn ClkIn~out0 D-flop } { 0.000ns 0.000ns 0.816ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ClkIn QOut D-flop 6.936 ns register " "Info: tco from clock \"ClkIn\" to destination pin \"QOut\" through register \"D-flop\" is 6.936 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn source 2.996 ns + Longest register " "Info: + Longest clock path from clock \"ClkIn\" to source register is 2.996 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ClkIn 1 CLK PIN_48 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 1; CLK Node = 'ClkIn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 160 88 256 176 "ClkIn" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.711 ns) 2.996 ns D-flop 2 REG LC_X1_Y4_N2 1 " "Info: 2: + IC(0.816 ns) + CELL(0.711 ns) = 2.996 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; REG Node = 'D-flop'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.527 ns" { ClkIn D-flop } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.76 % ) " "Info: Total cell delay = 2.180 ns ( 72.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.816 ns ( 27.24 % ) " "Info: Total interconnect delay = 0.816 ns ( 27.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.996 ns" { ClkIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.996 ns" { ClkIn ClkIn~out0 D-flop } { 0.000ns 0.000ns 0.816ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.716 ns + Longest register pin " "Info: + Longest register to pin delay is 3.716 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D-flop 1 REG LC_X1_Y4_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; REG Node = 'D-flop'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { D-flop } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.592 ns) + CELL(2.124 ns) 3.716 ns QOut 2 PIN PIN_56 0 " "Info: 2: + IC(1.592 ns) + CELL(2.124 ns) = 3.716 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'QOut'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.716 ns" { D-flop QOut } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 144 336 512 160 "QOut" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 57.16 % ) " "Info: Total cell delay = 2.124 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.592 ns ( 42.84 % ) " "Info: Total interconnect delay = 1.592 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.716 ns" { D-flop QOut } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.716 ns" { D-flop QOut } { 0.000ns 1.592ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.996 ns" { ClkIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.996 ns" { ClkIn ClkIn~out0 D-flop } { 0.000ns 0.000ns 0.816ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.716 ns" { D-flop QOut } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.716 ns" { D-flop QOut } { 0.000ns 1.592ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "D-flop DIn ClkIn -3.828 ns register " "Info: th for register \"D-flop\" (data pin = \"DIn\", clock pin = \"ClkIn\") is -3.828 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ClkIn destination 2.996 ns + Longest register " "Info: + Longest clock path from clock \"ClkIn\" to destination register is 2.996 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ClkIn 1 CLK PIN_48 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 1; CLK Node = 'ClkIn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ClkIn } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 160 88 256 176 "ClkIn" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.711 ns) 2.996 ns D-flop 2 REG LC_X1_Y4_N2 1 " "Info: 2: + IC(0.816 ns) + CELL(0.711 ns) = 2.996 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; REG Node = 'D-flop'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.527 ns" { ClkIn D-flop } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 72.76 % ) " "Info: Total cell delay = 2.180 ns ( 72.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.816 ns ( 27.24 % ) " "Info: Total interconnect delay = 0.816 ns ( 27.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.996 ns" { ClkIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.996 ns" { ClkIn ClkIn~out0 D-flop } { 0.000ns 0.000ns 0.816ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.839 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.839 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DIn 1 PIN PIN_58 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_58; Fanout = 1; PIN Node = 'DIn'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DIn } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 144 88 256 160 "DIn" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.061 ns) + CELL(0.309 ns) 6.839 ns D-flop 2 REG LC_X1_Y4_N2 1 " "Info: 2: + IC(5.061 ns) + CELL(0.309 ns) = 6.839 ns; Loc. = LC_X1_Y4_N2; Fanout = 1; REG Node = 'D-flop'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.370 ns" { DIn D-flop } "NODE_NAME" } } { "MyFirstProject.bdf" "" { Schematic "E:/php/MyFirstProject/MyFirstProject.bdf" { { 128 264 328 208 "D-flop" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 26.00 % ) " "Info: Total cell delay = 1.778 ns ( 26.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.061 ns ( 74.00 % ) " "Info: Total interconnect delay = 5.061 ns ( 74.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.839 ns" { DIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.839 ns" { DIn DIn~out0 D-flop } { 0.000ns 0.000ns 5.061ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.996 ns" { ClkIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.996 ns" { ClkIn ClkIn~out0 D-flop } { 0.000ns 0.000ns 0.816ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.839 ns" { DIn D-flop } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.839 ns" { DIn DIn~out0 D-flop } { 0.000ns 0.000ns 5.061ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 15:41:32 2008 " "Info: Processing ended: Wed May 07 15:41:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}