alarm1.vhd

VHDL写的数字钟

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity alarm1 is
  Port(reset:in std_logic;                
Min:in std_logic_vector(7 downto 0);
Alarm:out std_logic);                      -- ――输出的报时信号
End;
Architecture a of alarm1 is
 Begin
   Alarm<='1' when min="00000000" and reset='1'
 else '0';                             --――当分为0且清0
                               --信号无效时，输出高电平并持续至分不为0
end;