prev_cmp_topclock.map.qmsg

VHDL写的数字钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 08 16:54:32 2008 " "Info: Processing started: Sun Jun 08 16:54:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off topclock -c topclock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off topclock -c topclock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "topclock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file topclock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 topclock-one " "Info: Found design unit 1: topclock-one" {  } { { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 topclock " "Info: Found entity 1: topclock" {  } { { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file second1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 second1-a " "Info: Found design unit 1: second1-a" {  } { { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 second1 " "Info: Found entity 1: second1" {  } { { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "minute1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file minute1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 minute1-b " "Info: Found design unit 1: minute1-b" {  } { { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 minute1 " "Info: Found entity 1: minute1" {  } { { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hour1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hour1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hour1-a " "Info: Found design unit 1: hour1-a" {  } { { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 hour1 " "Info: Found entity 1: hour1" {  } { { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "day1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file day1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 day1-a " "Info: Found design unit 1: day1-a" {  } { { "day1.vhd" "" { Text "I:/topclock/day1.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 day1 " "Info: Found entity 1: day1" {  } { { "day1.vhd" "" { Text "I:/topclock/day1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alarm1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file alarm1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alarm1-a " "Info: Found design unit 1: alarm1-a" {  } { { "alarm1.vhd" "" { Text "I:/topclock/alarm1.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 alarm1 " "Info: Found entity 1: alarm1" {  } { { "alarm1.vhd" "" { Text "I:/topclock/alarm1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "topclock " "Info: Elaborating entity \"topclock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second1 second1:u1 " "Info: Elaborating entity \"second1\" for hierarchy \"second1:u1\"" {  } { { "topclock.vhd" "u1" { Text "I:/topclock/topclock.vhd" 45 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute1 minute1:u2 " "Info: Elaborating entity \"minute1\" for hierarchy \"minute1:u2\"" {  } { { "topclock.vhd" "u2" { Text "I:/topclock/topclock.vhd" 46 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour1 hour1:u3 " "Info: Elaborating entity \"hour1\" for hierarchy \"hour1:u3\"" {  } { { "topclock.vhd" "u3" { Text "I:/topclock/topclock.vhd" 47 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "day1 day1:u4 " "Info: Elaborating entity \"day1\" for hierarchy \"day1:u4\"" {  } { { "topclock.vhd" "u4" { Text "I:/topclock/topclock.vhd" 48 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alarm1 alarm1:u5 " "Info: Elaborating entity \"alarm1\" for hierarchy \"alarm1:u5\"" {  } { { "topclock.vhd" "u5" { Text "I:/topclock/topclock.vhd" 49 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "128 " "Info: Implemented 128 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "30 " "Info: Implemented 30 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Info: Implemented 28 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "70 " "Info: Implemented 70 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 08 16:56:46 2008 " "Info: Processing ended: Sun Jun 08 16:56:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:02:14 " "Info: Elapsed time: 00:02:14" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}