second1.vhd

来自「VHDL写的数字钟」· VHDL 代码 · 共 28 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;

Entity second1 is
 Port(clk,reset:in std_logic;
      Sec:buffer std_logic_vector(7 downto 0);      -- ――秒输出端
      Ensec:out std_logic		 --――秒计时器的进位，用来驱动分计时器
	 );             
End;

Architecture a of second1 is
Begin
 Process(clk,reset)
  Begin
   If reset='0' then
		sec<="00000000";          -- ――对秒计时器清0
   Elsif clk'event and clk='1' then
     if sec=59 then
		sec<="00000000";ensec<='1';    --――重复计数并产生进位   
     else 
		sec<=sec+1;ensec<='0';                               --以驱动下一级
     end if;
   end if;
End process;
End;