topclock.sim.rpt

VHDL写的数字钟

; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~23                            ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~23                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~24                            ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~24                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~28                            ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~28                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~29                            ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~29                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~30                            ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~30                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~31                            ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|_~31                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[5] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[4] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[4] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[3] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[3] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[2] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[2] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[1] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[1] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[0] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[0] ; |topclock|minute1:u2|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[0]                                ; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[0]                                     ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[1]                                ; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[1]                                     ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[2]                                ; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[2]                                     ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[3]                                ; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[3]                                     ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[4]                                ; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[4]                                     ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[5]                                ; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[5]                                     ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[6]                                ; |topclock|minute1:u2|lpm_add_sub:Add0|result_node[6]                                     ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~0                             ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~0                                  ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~3                             ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~3                                  ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]~4             ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]~4                  ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~5             ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~5                  ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~6             ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~6                  ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~7             ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~7                  ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]               ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[6]                    ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]               ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[5]                    ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]               ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[4]                    ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]               ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]                    ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]               ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]               ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~14                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~14                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~15                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~15                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~16                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~16                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~17                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~17                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~20                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~20                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~21                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~21                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~22                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~22                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~23                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~23                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~24                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~24                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~27                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~27                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~28                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~28                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~29                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~29                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~30                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~30                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~31                            ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|_~31                                 ; out0             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |topclock|minute1:u2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[0]                                  ; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[0]                                       ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[1]                                  ; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[1]                                       ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[2]                                  ; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[2]                                       ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[3]                                  ; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[3]                                       ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[4]                                  ; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[4]                                       ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[5]                                  ; |topclock|hour1:u3|lpm_add_sub:Add1|result_node[5]                                       ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]~0               ; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]~0                    ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]                 ; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[0]                      ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|_~0                               ; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|_~0                                    ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|_~3                               ; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|_~3                                    ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~5               ; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[3]~5                    ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]~6               ; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[2]~6                    ; out0             ;
; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]~7               ; |topclock|hour1:u3|lpm_add_sub:Add1|addcore:adder|unreg_res_node[1]~7