frequence.txt

基于FPGA设计的数字频率计

分频器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fdiv is
   Generic (  rate : integer :=10  );
   Port    (  f_in : In  std_logic;
	     f_out : Out std_logic );
end;
architecture behavioral of fdiv is
   signal cnt : integer range 0 to rate := 0;
   signal clk : std_logic:='0';
begin
   process (f_in)
   begin
      if f_in'event and f_in = '1' then
	 if cnt /= rate then
	    cnt <= cnt + 1;
	 else
	    cnt <= 1;
	    clk<=not clk;
	 end if;
      end if;
   end process;
f_out <= clk;
end behavioral;


闸门选择器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sele is
      port(se1,se10,se100:	in	std_logic;
	      f1hz,f10hz,f100hz:	in	std_logic;
		 fref:			out	std_logic;
		 dp1,dp2,dp3:		out	std_logic);
end sele;
architecture Behavioral of sele is
begin
  process (se1,se10,se100,f1hz,f10hz,f100hz)
   begin
      fref <= '0'; dp1 <= '0';dp2 <= '0';dp3 <= '0';
      if se1 = '1' then
	 fref <= f1hz;
	 dp1<= '1';
      elsif se10 = '1' then
	 fref <= f10hz;
	 dp2 <= '1';
      elsif se100 = '1' then
	 fref <= f100hz;
	 dp3 <='1';
      end if;
   end process;
end Behavioral;


测频控制器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control is
    Port ( Bsignal : in std_logic;
           Gate : out std_logic;
           Reset : out std_logic;
           latch : out std_logic);
end control;
architecture Behavioral of control is
  	signal G1,G2: std_logic:='0';
begin
process(Bsignal,G1)
  	begin
		if rising_edge(Bsignal) then
     	 	G1<=not G1;
		end if;
		if falling_edge(bsignal) then
			G2<=not G1;
		end if;	
end process;
		gate<=G1;
		latch<=G2;
		reset<=(not bsignal)and(not G1)and (G2);
end Behavioral;


频率计数器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (rst,clk : in std_logic;
      carry_in  : in std_logic;
      carry_out : out std_logic;
      count_out     : out std_logic_vector(3 downto 0));
end counter;
architecture Behavioral of counter is
	   signal count: std_logic_vector(3 downto 0):="0000";
begin
	process(rst,clk)
    	begin
		if rst='1' then
	    	count <= "0000";
		elsif clk'event and clk= '1' then
			if carry_in = '1' then
				if  count < "1001" then
		    		count <= count+1;
				else
		    		count <= "0000";
				end if;
	    		else
			null;
			end if;
		end if;	
  	end process;
      count_out<=count;
	  carry_out <= '1' when carry_in = '1' and count = "1001" else '0';
end Behavioral;



锁存器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity latch is
  port ( latchin	:	in std_logic;
         overin	:	in std_logic;
   	    numin1	:	in std_logic_vector(3 downto 0);
	    numin2	:	in std_logic_vector(3 downto 0);
	    numin3	:	in std_logic_vector(3 downto 0);
	    numin4	:	in std_logic_vector(3 downto 0);
	    numin5	:	in std_logic_vector(3 downto 0);
	    numin6	:	in std_logic_vector(3 downto 0);
	    overout	:	out std_logic;
	    numout1	:	out std_logic_vector(3 downto 0);
	    numout2	:	out std_logic_vector(3 downto 0);
	    numout3	:	out std_logic_vector(3 downto 0);
	    numout4	:	out std_logic_vector(3 downto 0);
	    numout5	:	out std_logic_vector(3 downto 0);
	    numout6	:	out std_logic_vector(3 downto 0));		 		
end latch;
rchitecture Behavioral of latch is
begin
  process(latchin)
    begin
   if rising_edge(latchin) then
   overout<=overin;
   numout1<=numin1;
   numout2<=numin2;
   numout3<=numin3;
   numout4<=numin4;
   numout5<=numin5;
   numout6<=numin6;
    end if;
  end process;
end Behavioral;

扫描显示控制译码系统
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multi is
       port(f1khz,q_over	:	in	std_logic;
	  	  dp1,dp2	:	in	std_logic;	
	      freq_value0,freq_value1	:	in	std_logic_vector(3 downto 0);
		 freq_value2,freq_value3	:	in	std_logic_vector(3 downto 0);
		 freq_value4,freq_value5	:	in	std_logic_vector(3 downto 0);
		 out0,out1,out2,out3,out4,out5:	out 	std_logic_vector(6 downto 0));
end multi;
architecture Behavioral of multi is
	signal 	sel		:	std_logic_vector(2 downto 0):="000";
	signal 	hide		:	std_logic; 
	signal 	data		:	std_logic_vector(3 downto 0);
	signal	led		:	std_logic_vector(6 downto 0);	
begin
	scan : process (f1khz)
   		begin
      		if rising_edge(f1khz) then
	 			if sel  = "101" then
	    			sel <= "000";
	 			else
	    			sel <= sel + 1;
	 			end if;
      		end if;
   		end process;
	mux:process(sel,freq_value0,freq_value1,freq_value2,freq_value3,freq_value4,freq_value5)
   		begin
      	case sel is
	 		when "000" =>	data <= freq_value0;
	 		when "001" =>	data <= freq_value1;
	 		when "010" =>	data <= freq_value2;
	 		when "011" =>	data <= freq_value3;
	 		when "100" =>	data <= freq_value4;
	 		when others =>	data <= freq_value5;
      	end case;
   		end process;
	bcd2led : process (hide,data)
   		begin
      	led <= "1111111";
      	if hide /= '1' then
	 		case data is
	    		when "0000" =>  led <= "0000001";	
	    		when "0001" =>  led <= "1001111";	
	    		when "0010" =>  led <= "0010010";	
	    		when "0011" =>  led <= "0000110";	
	    		when "0100" =>  led <= "1001100";	
	    		when "0101" =>  led <= "0100100";	
	    		when "0110" =>  led <= "0100000";	
	    		when "0111" =>  led <= "0001111";	
	    		when "1000" =>  led <= "0000000";
	    		when "1001" =>  led <= "0000100";
	    		when others =>  null;
	 		end case;
      	end if;
   		end process;
	fenpei:process(sel,led)
			begin
			out0<="1111111";
		     out1<="1111111";
		     out2<="1111111";
		     out3<="1111111";
		     out4<="1111111";
		     out5<="1111111";	
				case sel is
					when "000" => out0 <= led;
					when "001" => out1 <= led;
					when "010" => out2 <= led;
					when "011" => out3 <= led;
					when "100" => out4 <= led;
					when "101" => out5 <= led;
					when others => null;
				end case;
		end process;	
   	hide_zero:process (sel,q_over,dp1,dp2,freq_value5,freq_value4,freq_value3,freq_value2)
   		begin
      	hide <= '0';
      	case sel is
	 	when "101" =>
	    		if q_over = '0' and freq_value5 = "0000"
	       		then hide <= '1';
	    		end if;
	 	when "100" =>
	    		if q_over = '0' and freq_value5 = "0000"
				and freq_value4 = "0000"
	       		then hide <= '1';
	    		end if;
	 	when "011" =>
	    		if q_over = '0' and freq_value5 = "0000"
			    	and freq_value4 = "0000"
			    	and freq_value3 = "0000"
			    	and dp1 /= '1'
	       	then hide <= '1';
	    		end if;
	 	when "010" =>
	    		if q_over = '0' and freq_value5 = "0000"
			    	and freq_value4 = "0000"
			    	and freq_value3 = "0000"
			    	and freq_value2 = "0000"
			    	and dp1 /= '1'
			    	and dp2 /= '1'
	       	then hide <= '1';
	    		end if;
	 	when others =>
	    		null;
      	end case;
   		end process;
end Behavioral;



主函数

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter6 is
   port(Csignal	:	in 	std_logic;
	   clear		:	in	std_logic;
	   count_en	:	in	std_logic;
	   over		:	out	std_logic;
	   result1	:	out 	std_logic_vector(3 downto 0);
	   result2	:	out 	std_logic_vector(3 downto 0);
	   result3	:	out 	std_logic_vector(3 downto 0);
	   result4	:	out 	std_logic_vector(3 downto 0);
	   result5	:	out 	std_logic_vector(3 downto 0);
	   result6	:	out 	std_logic_vector(3 downto 0));
end counter6;
architecture structure of counter6 is
	component counter is
	     port(rst,clk   	: 	in 	std_logic;
      		carry_in  	: 	in 	std_logic;
      		carry_out 	: 	out 	std_logic;
      		count_out 	: 	out 	std_logic_vector(3 downto 0));
	 end component counter;
	 
	signal	carry1,carry2,carry3,carry4,carry5,carry6:	std_logic;
	signal	over1	:std_logic;		
begin
		U1 : counter Port map (     rst => clear,
				      clk => Csignal,
				 carry_in => count_en,
				carry_out => carry1,
				    count_out => result1   );
		U2 : counter Port map (     rst => clear,
				      clk => Csignal,
				 carry_in => carry1,
				carry_out => carry2,
				    count_out => result2   );
		U3 : counter Port map (     rst => clear,
				      clk => Csignal,
				 carry_in => carry2,
				carry_out => carry3,
				    count_out => result3   );
		U4 : counter Port map (     rst => clear,
				      clk => Csignal,
				 carry_in => carry3,
				carry_out => carry4,
				    count_out => result4   );
		U5 : counter Port map (     rst => clear,
				      clk => Csignal,
				 carry_in => carry4,
				carry_out => carry5,
				    count_out => result5   );
		U6 : counter Port map (     rst => clear,
				      clk => Csignal,
				 carry_in => carry5,
				carry_out => carry6,
				count_out => result6   );
process (clear,csignal)
   begin
      if clear = '1' then
	over1<= '0';
      elsif rising_edge(csignal) then
      over1 <= carry6 or over1;
      end if;
   end process;
   over<=over1;
end structure;