_primary.vhd

来自「正弦信号发生器程序,用VERILOG写出。」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity sin_top is
    port(
        D               : out    vl_logic_vector(7 downto 0);
        clk             : in     vl_logic;
        WR_n            : out    vl_logic;
        rst             : in     vl_logic
    );
end sin_top;