spi_master_interface.v

a verilog prigram for SPI

module spi_master_interface(clk,reset,wr_tr_en,start,spi_start,
                            /*ss_in_n,*/config_done,tr_load,tx_empty,
                            int_n,rd_n,load_rr,data_byte,data_byte_int,
                            data,data_in,tran_done);
                     
   input clk,reset,spi_start,config_done,tr_load,tx_empty,
         int_n,rd_n,load_rr;
   input [31:0]data_in;
   input [1:0]data_byte;
   output [1:0]data_byte_int;
   output [7:0]data; 
   output wr_tr_en,start,tran_done/*,ss_in_n*/;

	//output [2:0]i;
   
   reg wr_tr_en,start/*,ss_in_n*/;
   //reg [1:0]j;
   reg [7:0]data_out;
   reg [1:0]data_byte_int;
   reg [31:0]tx_data;
   reg load_rr_delay;
   
   parameter idle=0,wait_config=1,enable_wr_tr=2,write_tr=3,
             trans_data=4,transfer=5,end_tran=6,end_cycle=7;
   reg [2:0]state,next_state;
   
   wire load_rr_fe;
   assign load_rr_fe=(~load_rr)&load_rr_delay;
   assign data=(!config_done|!rd_n|load_rr)?8'bzzzzzzzz:data_out;
   assign tran_done=(state==end_tran)?1:0;     
   
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            state<=idle;
         else state<=next_state;
      end
      
   always @(state,spi_start,config_done,tr_load,tx_empty,
            int_n,data_byte_int,data_byte,load_rr)
      begin
         case (state)
            idle: begin
                     if (spi_start)
                        next_state<=wait_config;
                     else next_state<=idle;
                  end
            wait_config: begin
                            if (config_done)
                               next_state<=enable_wr_tr;
                            else next_state<=wait_config;
                         end
            enable_wr_tr: next_state<=write_tr;
            write_tr: begin
                         //i<=0;
                         if (tr_load)
                            next_state<=transfer;
                         else next_state<=write_tr;
                      end
            trans_data:begin
                          if (int_n) 
                             next_state<=transfer;
                          else next_state<=trans_data;
                       end
            transfer: begin
                         if (((!int_n)&(tx_empty))|(load_rr))
                            begin
                               //i<=i+1;
                               if (load_rr==1)
                                  if (data_byte_int==data_byte)
                                     next_state<=end_tran;
                                  else next_state<=transfer;
                               else if (data_byte_int==data_byte)
                                       next_state<=transfer;
                                    else 
                                       next_state<=trans_data;
                            end
                         else next_state<=transfer;
                      end
            end_tran: next_state<=end_cycle;
            end_cycle: next_state<=idle; 
            default: next_state<=idle;
         endcase
      end
      
      always @(posedge clk or negedge reset)
         begin
            if (!reset)
               begin
                  wr_tr_en<=0;
                  //ss_in_n<=1;
				      start<=0;
				      data_out<=8'b00000000;
						//i=1;
               end
            else
               begin
                  case (next_state)
                     idle: wr_tr_en<=0;
                     wait_config: wr_tr_en<=0;
                     enable_wr_tr: begin
                                     if (config_done)
                                        begin
                                           data_out<=tx_data[7:0];
                                           wr_tr_en<=1;
                                        end
                                     else wr_tr_en<=0;
                                   end
                     write_tr: start<=0;
                     trans_data: begin
                                    if (config_done)
                                       begin

														//i=i+1;
                                          case(data_byte_int)
                                             0: data_out<=tx_data[15:8];
                                             1: data_out<=tx_data[23:16];
                                             2: data_out<=tx_data[31:24];
                                             default: start<=1;
                                          endcase
                                       end
                                    //else data_out<=data_out;
                                 end
                     transfer: begin
                                  //i<=i+tx_int;
                                  wr_tr_en<=0;
                                  start<=1;
                               end
                     end_tran: start<=0;
                     end_cycle: start<=0;
                     default: start<=0;
                  endcase
               end
      end
   
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            tx_data<=0;
         else if (spi_start)
        	   tx_data<=data_in;
      end

   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            load_rr_delay<=0;
         else load_rr_delay<=load_rr;
      end

	
	always @(negedge clk)

		begin
         if (!reset)
            data_byte_int<=0;
         else if (start==0)
			   data_byte_int<=0;
			else if (load_rr_fe)
            data_byte_int<=data_byte_int+1;
	   end
                  
endmodule