state_controller.v

a verilog prigram for SPI

			      addr<=spicr_addr;
               //last_data_tr<=8'b00000000;
               //last_data_rr<=8'b00000000;
               //last_tr_flag<=0;
               //last_rr_flag<=0;
               load_rr<=0;
               tr_load<=0;
            end
         else
            begin
               case (next_state)
                  read_bb: {wr_n,rd_n}<=2'b11; 
                  chk_bb: {wr_n,rd_n}<=2'b11; 
                  idle: {wr_n,rd_n}<=2'b11;  
                  write: begin
                            case (address)
                               spicr_addr: begin
                                              addr<=spicr_addr;
                                              //spien=1,inten=1,start=0,clkdiv=2'b00
                                              //cpha=0,cpol=0,rec_cpol=1;
                                              data_in<=8'b11000001;
                                              wr_n<=0;
                                              spi_config_reg<=1;
                                              address<=spissr_addr;
                                           end
                               spissr_addr: begin
                                               addr<=spissr_addr;
                                               data_in<=8'b10000000;
                                               wr_n<=0;
                                               spi_config_reg<=1;
                                               address<=spitr_addr;
                                            end
                               spirr_addr: begin
                                              addr<=spirr_addr;
                                              //addr_data<=8'bzzzzzzzz;
                                              rd_n<=0;
                                              spi_config_reg<=1;
                                           end             
                               default: {wr_n,rd_n}<=2'b11; 
                            endcase
                         end
               wait_tr: address<=spitr_addr; 
               write_tr: begin
                            addr<=spitr_addr;
                            //addr_data<=8'b11001001;
                            wr_n<=0;
                            spi_config_reg<=1;
                         end
               addr_decode: begin
                               //if (address==spitr_addr)
                               //   if (last_data_tr!=data)
                               //      last_tr_flag<=1;
                                  //else last_tr_flag<=0;
                               //else spi_config_reg<=1;

										 spi_config_reg<=1;
                            end               
               data_trs: begin
                            if (address==spitr_addr)
                               begin
										 	 /*if (last_data_tr!=data)
                                     last_tr_flag<=1;
                                  else last_tr_flag<=0;*/
                               //else spi_config_reg<=1;
                                  //last_data_tr<=data;
                                  tx_empty_reset<=0;
                                  //if ((start==1)||(wr_tr_en==1))
                                  //   tx_empty_reset<=0; //reset tx_empty
                                  //else tx_empty_reset<=tx_empty_reset;
                               end
                            else //last_data_tr<=last_data_tr;
                            if (address==spirr_addr)
                               begin
                                  load_rr<=1;
                                  //tx_empty_reset<=0;
                                  rec_full_reset<=0;    //reset rec_full
                               end
                            else spi_config_reg<=1;
                         end 
               end_cycle: begin
                             //initial start signal
                             //if (address==spissr_addr)
                             //   start_reset<=0;
                             //else {wr_n,rd_n}<=2'b11;
                             //if (address==spirr_addr)
                             //   begin
                             //      if (last_data_rr!=data)
                             //         last_rr_flag<=1;
                             //      else last_rr_flag<=0;
                             //      last_data_rr<=data;
                             //   end
                             //else {wr_n,rd_n}<=2'b11;
                             
                             if (address==spitr_addr)
                                begin
                                   config_done<=1;
											  //last_data_tr<=data;
                                   //tx_empty_reset<=0;
                                   //if ((start==0)&&(wr_tr_en==1))
                                   if ((start==0)&&(wr_tr_en==1))
                                      tr_load<=1;
                                   else {wr_n,rd_n}<=2'b11;
                                end
                             else {wr_n,rd_n}<=2'b11;
                             wr_n<=1;
                             rd_n<=1;
                             spi_config_reg<=0;
                          end
               wait_start: begin
                              //tr_load<=0;
                              //start_reset<=1;
                              load_rr<=0;
                              //spierr_reset<=1;
                              //spien_reset<=1;
                              tx_empty_reset<=1;  //disable tx_empty_reset to enable int_n
                              rec_full_reset<=1;
                           end
               wait_int: begin
                            //{wr_n,rd_n}<=2'b11;
                            //wr_tr_en_reg<=0;
                            /*if (int_n==0)
                               {wr_n,rd_n}<=2'b10;
                            else {wr_n,rd_n}<=2'b11;*/
                            tr_load<=0;
                            //load_rr<=0;
                            if (tx_empty==0)
                               tx_empty_reset<=1;
                            else {wr_n,rd_n}<=2'b11;
                         end
               //read_spierr: {wr_n,rd_n}<=2'b10; 
               chk_int: begin
                              if (tx_empty==1) 
                                 begin
                                       //if (last_tr_flag==0)
                                       //   start_reset<=0;
                                       //else 
                                       //   begin
                                     address<=spitr_addr;
                                             //start_reset<=1;
                                       //   end
                                     end
                                  //else {wr_n,rd_n}<=2'b11;
                               else {wr_n,rd_n}<=2'b11; 
                            end
               chk_rec_full: begin
                                if (rec_full==1)
                                   address<=spirr_addr;
                                else {wr_n,rd_n}<=2'b11;
                             end
               /*write_spireset: spierr_reset<=0;
               reset_spierr: {wr_n,rd_n}<=2'b11;
               //read_err: {wr_n,rd_n}<=2'b10;
               det_err: {wr_n,rd_n}<=2'b11;
               reset_spien: spien_reset<=0;
               end_spi: {wr_n,rd_n}<=2'b11;
               */
               default: {wr_n,rd_n}<=2'b11;
            endcase
         end
      end
      
   //always @(last_tr_flag,tx_empty) 
   //   wr_tr<=last_tr_flag&tx_empty;
      
   //generate config_done signal
   /*
   always @(reset,start,wr_tr_en)
      begin
         if (!reset)
            config_done<=0;
         else if (start==0)
                  if (wr_tr_en==0)
                     config_done<=0;
                  else config_done<=1;
         else config_done<=1;
      end
   */
endmodule