state_controller.v

a verilog prigram for SPI

module state_controller(clk,reset,spi_config,config_done,tr_load,wr_n,
                        rd_n,addr,data,/*spien_reset,*/int_n,start,/*start_reset,*/
                        tx_empty,rec_full,wr_tr_en,bb,/*spierr,*/load_rr,
                        tx_empty_reset,rec_full_reset/*,spierr_reset*/);
   
   input clk,reset;
   inout spi_config;                       //active high spi config signal
   output config_done;                     //config_done is aserted when config is completed
   output tr_load;                         //transfer reg is loaded when tr_load is high
   output wr_n,rd_n;
   output [7:0]data;
   output [2:0]addr;
   //output addr_sel;                        //addr driven select signal
   //output data_sel;                        //data driven select signal
   //output spien_reset;                     //spien will be reset when spien_set is high
   //output spierr_reset;
   input int_n;                            //active low interrupt request
   input start;                            //start transfer
   //output start_reset;                     //start will be set when start_set is high
   //output start_sel;                       //start driven select signal
   input tx_empty;                         //flag indicating that spitr is empty
   input rec_full;                         //flag indicating that spirr is full
   output tx_empty_reset;
   output rec_full_reset;
   input wr_tr_en;                         //to enable writing spitr when wr_tr_en is high
   //output wr_tr;                           //transfer data will be update when wr_tr is high
   input bb;                               //bus busy signa
   //input spierr;                           //spi error signal
   output load_rr;                         //load receive data to mcu when load_rr is high
	//output last_tr_flag,last_rr_flag;
	//output [2:0]address;
	//output [7:0]last_data_tr,last_data_rr;
   
   parameter read_bb=0,chk_bb=1,idle=2,write=3,wait_tr=4,
             write_tr=5,addr_decode=6,data_trs=7,end_cycle=8,
             wait_start=9,wait_int=10,chk_int=11,
             chk_rec_full=12/*,write_spireset=13,reset_spierr=14,
             det_err=15,reset_spien=16,end_spi=17*/;
             
   //parameter base_addr=8'b00000000; //base address
   parameter spisr_addr=3'b000; //address of status reg
   parameter spicr_addr=3'b001; //address of control reg
   parameter spissr_addr=3'b010;//address of slave select reg
   parameter spitr_addr=3'b011; //address of transmit reg
   parameter spirr_addr=3'b100; //address of receive reg
   
   //output [4:0]state,next_state;
	reg [3:0]state,next_state;
   
   reg [7:0]data_in;
   reg [2:0]addr;
   //reg spien_reset;
   //reg spierr_reset;
   //reg wr_tr;
   reg load_rr;
   
   reg [2:0]address;
   //reg [7:0]last_data_tr,last_data_rr;     //store transmit data and receive data
   //reg last_tr_flag,last_rr_flag;          //flag asserted when last data is updated
   
   reg spi_config_reg;
   reg config_done;
   reg tr_load;
   reg wr_n,rd_n;
   //reg start_reset;
   reg tx_empty_reset;
   reg rec_full_reset;
   //reg start_reg;
   //reg wr_tr_en_reg;
	//wire last_tr_en;
	
   
   assign spi_config=spi_config_reg;
   //assign start=start_reg;
   //assign wr_tr_en=wr_tr_en_reg;
   
   assign data=(~config_done)?data_in:8'bzzzzzzzz;
   //assign start_set=(~last_tr_flag)&tx_empty;
   //assign start_sel=(~last_tr_flag)&tx_empty;
   
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
               state<=read_bb;
               //next_state<=idle;
         else state<= next_state;
      end

   always @(state,bb,wr_tr_en,start,int_n,tx_empty,
            rec_full,/*last_tr_flag,*/address)
      begin
         case (state)
            read_bb: next_state<=chk_bb;
            chk_bb: begin
                        if (bb==1)
                           next_state<=read_bb;
                        else next_state<=idle;
                     end
            idle: next_state<=write;
            write: next_state<=addr_decode;
            wait_tr: begin
                        if (wr_tr_en==1)
                        next_state<=write_tr;
                        else next_state<=wait_tr;
                     end
            write_tr: next_state<=addr_decode;
            addr_decode: next_state<=data_trs;
            data_trs: next_state<=end_cycle;
            end_cycle: begin
                          case (address)
                             spissr_addr: next_state<=write;
                             spirr_addr: next_state<=wait_start;
                             spitr_addr: begin
                                            if ((start==0)&&(wr_tr_en==0))
                                               next_state<=wait_tr;
                                            else if ((start==0)&&(wr_tr_en==1))
                                               next_state<=wait_start;
                                            else next_state<=chk_rec_full;
                                         end
                             default: next_state<=read_bb;
                          endcase
                       end
            wait_start: begin
                           if (start==1)
                              next_state<=wait_int;
                           else
                              begin 
                                 if (wr_tr_en==1)
                                    next_state<=wait_start;
                                 else next_state<=wait_tr;
                              end
                        end
            wait_int: begin
                         if (int_n==0)
                               next_state<=chk_int;
                         else next_state<=wait_int;
                     end
            //read_spierr: next_state<=det_spierr; 
            chk_int: begin
                        if (tx_empty==1)
                            //if (last_tr_flag==1)
                            next_state<=write_tr;
                            //else 
                            //   next_state<=det_rec_full;
                        else next_state<=chk_rec_full;
                     end
            chk_rec_full: begin
                             if (rec_full==1)
                                next_state<=write;
                             else next_state<=wait_int;
                          end
            /*write_spireset: next_state<=reset_spierr;
            reset_spierr: next_state<=det_err;
            read_err:next_state<=det_err;
            det_err: begin
                         if (spierr==1)
                            next_state<=write_spireset;
                         else next_state<=reset_spien;
                      end
            reset_spien: next_state<=end_spi;
            end_spi: next_state<=wait_tr;*/                                        
            default: next_state<=idle;
         endcase
      end 
   
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            begin
               spi_config_reg<=0;
               config_done<=0;
               data_in<=8'b00000000;
               wr_n<=1;
               rd_n<=1;
               //start_reg<=0;
               //start_reset<=0;
               //spien_reset<=1;
               //spierr_reset<=1;
               tx_empty_reset<=0;
               rec_full_reset<=0;
               address<=spicr_addr;