rec_shift.v

a verilog prigram for SPI

module rec_shift(miso,shift_en,data_out,rec_load,/*sclk_re,sclk_fe,*/
                 cpol,rec_cpol,/*ss_in_int,*/sclk,reset);
                 
   //shift control and data
   input miso;                           //Serial data in
   input shift_en;                       //Active low shift
   
   //parallel data out
   output [7:0]data_out;                 //Shifted data
   output rec_load;                      //load signal to uC register
   
   //rising edge and falling SCK edges
   //input sclk_re;                         //rising edge of SCK
   //input sclk_fe;                         //falling edge of SCK
   
   //mcu configuration for receive clock polarity
   input cpol;                           //spi clock polarity
   input rec_cpol;                       //receive clock polarity
   
   //input ss_in_int;
   
   input sclk,reset;
   
   reg [7:0]data_int;
   reg shift_in;                         //data to be shifted in
   reg miso_neg;                         //data clocked on neg SCK
   reg miso_pos;                         //data clocked on pos SCK
   
   reg [2:0]rec_cnt_int;                 //internal bit count
   wire [2:0]rec_cnt;                    //bit count
   
   assign rec_cnt=rec_cnt_int;
   assign data_out={data_int[6:0],shift_in};
   assign rec_load=((shift_en==0)&&
                      ((rec_cnt==0)&&(cpol==0)&&(rec_cpol==1)&&(sclk==1))
                    ||((rec_cnt==0)&&(cpol==1)&&(rec_cpol==1)&&(sclk==1))
                    ||((rec_cnt==0)&&(cpol==0)&&(rec_cpol==0)&&(sclk==0))
                    ||((rec_cnt==7)&&(cpol==1)&&(rec_cpol==0)&&(sclk==0)))
                    ?1:0;
   
   always @(posedge sclk or negedge reset)
      begin
         if (!reset)
            data_int<=8'b00000000;
         else if (!shift_en)
                 data_int<={data_int[6:0],shift_in};
              //else data_int<=data_int;
      end

   //The MISO signal is clocked on both the rising and falling edges of SCK. The output
   //of both these registers is then multiplexed with the RCV_CPOL control bit choosing
   //which data is the valid data for the system. This data is then the input to the
   //shift register.
   
   //SCK rising edge register
   always @(posedge sclk or negedge reset)
      begin
         if (!reset)
            miso_pos<=0;
         /*else if (!ss_in_int)
            miso_pos<=0;*/
         else miso_pos<=miso;
      end
      
   //SCK falling edge register
   always @(negedge sclk or negedge reset)
      begin
         if (!reset)
            miso_neg<=0;
         /*else if (!ss_in_int)
            miso_neg<=0;*/
         else miso_neg<=miso;
      end

   //RCV_CPOL multiplexor to determine shift in data
   always @(rec_cpol,miso_neg,miso_pos)
      begin
         if (rec_cpol===1)
            shift_in<=miso_pos;
         else 
            shift_in<=miso_neg;
      end
      
   //Count bits loading into the SPI receive shift register based on SCK
   //assert RCV_LOAD when bit count is 0
   always @(posedge sclk or negedge reset)
      begin
         if (!reset)
            rec_cnt_int<=0;
         else if (shift_en)
            rec_cnt_int<=0;
         else
            rec_cnt_int<=rec_cnt_int+1;
      end

endmodule