spi_master.v

a verilog prigram for SPI

module spi_master(clk,reset,config_done,tr_load,tx_empty,
                  rec_full,int_n,wr_tr_en,load_rr,start,
                  data,rd_n,ss_n,mosi,miso,sck/*,ss_in_n*/);
                  
   input clk,reset;
   output config_done;
   output tr_load;
   inout tx_empty;
   inout rec_full;
   inout int_n;
   input wr_tr_en;
   output load_rr;
   input start;
   output rd_n;
   output mosi;
   input miso;
   inout sck;
   //input ss_in_n;
   inout [7:0]data;
   output [7:0]ss_n;
   
   wire spi_start,spien,rec_load,ssn,/*ss_in_int,*/tx_empty_reset,
        rec_full_reset,cpha,cpol,rec_cpol,done;
   wire [1:0]clkdiv;     
   wire [7:0]spitr,spissr,receive_data;     
   
   state_controller_top state_ctrl(.clk(clk),.reset(reset),.data(data),.int_n(int_n),
                                   .start_set(start),.spien(spien),.rec_load(rec_load),
                                   .ss_n(ssn),.tx_empty(tx_empty),.rec_full(rec_full),
                                   .tx_empty_reset(tx_empty_reset),.clkdiv(clkdiv),
                                   .rec_full_reset(rec_full_reset),.cpha(cpha),.cpol(cpol),
                                   .spitr(spitr),.spissr(spissr),.rec_cpol(rec_cpol),
                                   .receive_data(receive_data),.start(spi_start),.rd_n(rd_n),
                                   .config_done(config_done),.tr_load(tr_load),.load_rr(load_rr),
                                   .done(done),/*.ss_in_int(ss_in_int),*/.wr_tr_en(wr_tr_en));
                
   spi_interface spi_int(.clk(clk),.reset(spien),.clkdiv(clkdiv),.cpha(cpha),.cpol(cpol),
                         .mosi(mosi),.miso(miso),.rec_cpol(rec_cpol),.tx_empty(tx_empty),
                         .tx_empty_reset(tx_empty_reset),.rec_full_reset(rec_full_reset),
                         .tx_data(spitr),.rec_full(rec_full),.ss_n_int(ssn),.ss_n(ss_n),
                         /*.ss_in_int(ss_in_int),.ss_in_n(ss_in_n),*/.ss_mask_reg(spissr),
                         .start(spi_start),.done(done),.rec_data(receive_data),
                         .rec_load(rec_load),.sck(sck));
                         
endmodule