tx_shift.v

来自「a verilog prigram for SPI」· Verilog 代码 · 共 38 行

module tx_shift(sys_clk,sclk,reset,load,data_in,shift_en,
                shift_in,mosi/*,ss_in_int*/);
                
   input sys_clk;                     //system clock
   input sclk,reset;                        
   input load;                        //Data load enable
   input [7:0]data_in;                //Data to load in
   input shift_en;                    //Shift enable
   input shift_in;                    //Serial data in
   output mosi;                       //Shift serial data out
   //input ss_in_int;                   //another master is on bus
   
   reg [7:0]data_int;
   reg mosi_int;
   
   assign mosi=/*ss_in_int?*/mosi_int/*:1'bz*/;
   
   always @(posedge sclk or negedge reset)
      begin
         if (!reset)
            data_int<=8'b00000000;
         else if (load)
                 data_int<=data_in;
         else if (shift_en)
                 data_int<={data_int[6:0],shift_in};
              //else data_int<=data_int;
      end
      
   always @(posedge sys_clk or negedge reset)
      begin
         if (!reset)
            mosi_int<=0;
         else
            mosi_int<=data_int[7];
      end
   
endmodule