state_controller_top.v

a verilog prigram for SPI

module state_controller_top(clk,reset,data,int_n,start_set,start,spien,done,
                            rec_load,ss_n,/*ss_in_int,*/tx_empty,tx_empty_reset,
                            rec_full,rec_full_reset,clkdiv,cpha,cpol,
                            spitr,spissr,rec_cpol,receive_data,config_done,
                            tr_load,wr_tr_en,load_rr,rd_n);

   input clk,reset;
   inout [7:0]data;
   inout int_n;
   input start_set;
   inout start;
   inout spien;
   input done;
   input rec_load;
   input ss_n;
   //input ss_in_int;
   input tx_empty;
   output tx_empty_reset;
   input rec_full;
   output rec_full_reset;
   output [1:0]clkdiv;
   output cpha;
   output cpol;
   output [7:0]spitr;
   output [7:0]spissr;
   output rec_cpol;
   input [7:0]receive_data;
   output tr_load;
   output config_done;
   input wr_tr_en;
   //output wr_tr;
   //input bb;
   //input spierr;
   output load_rr;
   output rd_n;
   
   wire spiconfig,wrn,/*spien_rst,start_out,start_rst,spierr_rst,spierror,*/spibb;
   wire [2:0]address;
   
   mcu_interface uc_interface(.clk(clk),.reset(reset),.spi_config(spiconfig),
                              .addr(address),.data(data),.wr_n(wrn),.rd_n(rd_n),
                              .int_n(int_n),.spien(spien),/*.spien_reset(spien_rst),*/
                              .start(start),.start_set(start_set/*start_out*/),.rec_load(rec_load),
                              .spissr(spissr),.ss_n(ss_n),/*.ss_in_int(ss_in_int),*/
                              .tx_empty(tx_empty),.tx_empty_reset(tx_empty_reset),
                              .rec_full(rec_full),.rec_full_reset(rec_full_reset),
                              .clkdiv(clkdiv),.cpha(cpha),.cpol(cpol),.spitr(spitr),
                              .rec_cpol(rec_cpol),.receive_data(receive_data),.done(done),
                              /*.spierr_reset(spierr_rst),.spi_err(spierror),*/.spi_bb(spibb));
    
   state_controller state_ctrl(.clk(clk),.reset(reset),.spi_config(spiconfig),.wr_n(wrn),
                               .rd_n(rd_n),.addr(address),.data(data),/*.spien_reset(spien_rst),*/
                               .int_n(int_n),.start(start),/*.start_reset(start_rst),*/.config_done(config_done),
                               .tr_load(tr_load),.tx_empty(tx_empty),.rec_full(rec_full),.wr_tr_en(wr_tr_en),
                               .bb(spibb),/*.spierr(spierror),*/.load_rr(load_rr),.tx_empty_reset(tx_empty_reset),
                               .rec_full_reset(rec_full_reset)/*,.spierr_reset(spierr_rst)*/);
                               
   //mux_2 mux2(.start(start_set),.start_reset(start_rst),.start_sel(start_rst),
   //           .start_out(start_out));
              
endmodule