mcu_interface.v

a verilog prigram for SPI

               //rec_full_rst<=0;
               
               //initialize data bus
               data_out<=8'b00000000;
               
               //address<=base_addr;
               data_oe<=0;
            end
         else
            begin
               case (next_state)
                  idle: begin
                           /*case ({wr_n,rd_n})
                              2'b01: spierr_reset<=0;
                              2'b10: begin
                                        data_out[6]<=spierr;
                                        data_out[5]<=bb;
                                        data_oe<=1;
                                     end
                              default: data_oe<=0;
                           endcase*/
                           /*if ({wr_n,rd_n}==2'b10)
                              begin
                                 data_out[6]<=spierr;
                                 data_out[5]<=bb;
                                 data_oe<=1;
                              end
                           else data_oe<=0;*/
                           data_oe<=0;    
                        end
                  addr_decode: begin
                                  case (address)
                                     spisr_addr: begin
                                                    stat_en<=1;
                                                    ctrl_en<=0;
                                                    ssr_en<=0;
                                                    tr_en<=0;
                                                    rr_en<=0;
                                                 end
                                     spicr_addr: begin
                                                    stat_en<=0;
                                                    ctrl_en<=1;
                                                    ssr_en<=0;
                                                    tr_en<=0;
                                                    rr_en<=0;
                                                 end
                                     spissr_addr: begin
                                                     stat_en<=0;
                                                     ctrl_en<=0;
                                                     ssr_en<=1;
                                                     tr_en<=0;
                                                     rr_en<=0;
                                                  end
                                     spitr_addr: begin
                                                    stat_en<=0;
                                                    ctrl_en<=0;
                                                    ssr_en<=0;
                                                    tr_en<=1;
                                                    rr_en<=0;
                                                 end
                                     spirr_addr: begin
                                                    stat_en<=0;
                                                    ctrl_en<=0;
                                                    ssr_en<=0;
                                                    tr_en<=0;
                                                    rr_en<=1;
                                                 end
                                     default: data_oe<=0;        
                                  endcase
                               end
                  data_trs: begin
                               if (!rd_n)
                                  data_oe<=1;
                               //else data_oe<=data_oe;
                               case (1'b1)
                                  ctrl_en: begin
                                              if (!wr_n)
                                                 begin
                                                    spi_en<=data_in[7];
                                                    inten<=data_in[6];
                                                    start_ctrl<=data_in[5];
                                                    clkdiv_ctrl<=data_in[4:3];
                                                    cpha_ctrl<=data_in[2];
                                                    cpol_ctrl<=data_in[1];
                                                    rcv_cpol<=data_in[0];
                                                 end
                                              else if (!rd_n)
                                                      data_out<={spi_en,inten,start_ctrl,clkdiv_ctrl,
                                                                 cpha_ctrl,cpol_ctrl,rcv_cpol};
                                              else data_oe<=0;
                                           end                   
                                  stat_en: begin
                                              /*if (!wr_n)
                                                 if (data_in[6]==0)
                                                    spierr_reset<=0;
                                                 else spierr_reset<=1;
                                              else*/ if (!rd_n)
                                                      data_out<={dt,1'b0,bb,intn,
                                                                 tx_empty,rec_full,2'b00};
                                              else data_oe<=0;
                                           end
                                  tr_en: begin
                                            if (!wr_n)
                                               begin
                                                  spitx<=data_in;
                                                  //tx_empty_rst<=0;
                                               end
                                            else if (!rd_n)
                                                    data_out<=spitx;
                                            else data_oe<=0;
                                         end
                                  rr_en: begin
                                             if (!rd_n)
                                                begin
                                                   data_out<=spirr;
                                                   //rec_full_rst<=0;
                                                end
                                             else data_oe<=0;
                                         end
                                  ssr_en: begin
                                             if (!wr_n)
                                                spiss<=data_in;
                                             else if (!rd_n)
                                                     data_out<=spiss;
                                             else data_oe<=0;
                                          end
                                  default: data_oe<=0;
                               endcase
                            end
                  end_cycle: start_ctrl<=0;
                  default: start_ctrl<=0;
               endcase
            end
      end      
              
   //status reg
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            begin
               bb<=0;
               //spierr<=0;
               intn<=0;
               dt<=0;
            end
         else
            begin
               //bus busy asserts when ss_n is asserted
               if (!ss_n) bb<=1;
               else bb<=0;
               
               //spi error asserts when the input slave select is asserted
               //once asserted, this bit stays asserted until written to by the uC
               //if (!spierr_reset) spierr<=0;
               //else if (!ss_in_int) spierr<=1;
               //else spierr<=spierr;
               
               //interrupt is asserted when the SPITR is empty or an error occurs
               //IF interrupts are enabled interrupt service routine should read 
               //status register to determine cause of interrupt.
               if (/*(!spierr_reset)|*/(!tx_empty_reset)|(!rec_full_reset))
                  intn<=1;
               else if (inten==1)
                       if (/*(spierr)|*/(start&tx_empty)|(start&rec_full))
                          intn<=0;
                       else //intn<=intn;
                          intn<=1;
                       
               //data transfer bit asserts when done is asserted
               if (done) dt<=1;
               else dt<=0;
            end
      end
      
   //receive reg
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            spirr<=8'b00000000;
         else if (!spien)
            spirr<=8'b00000000;
         else if (rec_load)
            spirr<=receive_data;
         //else spirr<=spirr;
      end
      
endmodule