mcu_interface.v

a verilog prigram for SPI

module mcu_interface(clk,reset,spi_config,data,addr,rd_n,wr_n,
                     spien,/*spien_reset*/,int_n,start,start_set,done,
                     rec_load,spissr,ss_n,/*ss_in_int,*/tx_empty,
                     tx_empty_reset,rec_full,rec_full_reset,clkdiv,
                     cpha,cpol,spitr,rec_cpol,receive_data,/*spierr_reset,
                     spi_err,*/spi_bb);

   //mcu interface port
   input clk,reset;
   input spi_config;                 //active high spi configure
   input [2:0]addr;                  //address of register
   inout [7:0]data;                  //data in register
   input rd_n;                       //active low read strobe
   input wr_n;                       //active low write strobe
   inout int_n;                      //active low interrupt request
   
   //spi_controller interface
   inout spien;                      //enable the spi_interface
   //input spien_reset;                //spi_en will be set when spi_en_set is high
   //input spierr_reset;               //spierr will be reset when spierr_reset is low
   inout start;                      //start transfer
   input start_set;                  //start will be set when start_set is high
   input done;                       //indicating transfer is completed
   input rec_load;                   //load signal to receive reg
   inout [7:0]spissr;                //spi slave select reg
   input ss_n;                       //active low slave select signal
   //input ss_in_int;                  //internal sampled version of ss_in_n 
                                     //needed by mcu to generate an interrupt                 
   input tx_empty;                   //flag indicating that spitr is empty
   input tx_empty_reset;             //tx_empty flag reset when spitr is written
   input rec_full;                   //flag indicating that spirr is full
   input rec_full_reset;             //rec_full flag reset when spirr has new data
   
   //sck_logic interface
   inout [1:0]clkdiv;                //sets the clock divisor for sck clock
   inout cpha;                       //sets clk phase for output sck
   inout cpol;                       //sets clk polarity for output sck
   
   //receive and transmit shift interface
   inout [7:0]spitr;                 //spi transmit reg bus
   inout rec_cpol;                   //clk polarity for incoming data
   input [7:0]receive_data;          //data received bus
   
   output /*spi_err,*/spi_bb;
   
   //parameter base_addr=8'b00000000;  //base address
   parameter spisr_addr=3'b000; //address of status reg
   parameter spicr_addr=3'b001; //address of control reg
   parameter spissr_addr=3'b010;//address of slave select reg
   parameter spitr_addr=3'b011; //address of transmit reg
   parameter spirr_addr=3'b100; //address of receive reg
   
   parameter idle=0,addr_decode=1,data_trs=2,end_cycle=3;
  
   reg [7:0]data_out;                //holds the data to be output on the data bus
   reg [7:0]data_in;                 //holds the data to be input to the chip
   reg data_oe;                      //allows data to be output on the data bus
   
   //reg enable signal
   reg ctrl_en;                      //control reg is addressed
   reg stat_en;                      //status reg is addressed
   reg ssr_en;                       //slave select reg is addressed
   reg tr_en;                        //transmit data reg is addressed
   reg rr_en;                        //receive data reg is addressed
   
   //reg reset signal
   //reg spierr_reset;                 //writing 0 this bit in the status register
                                     //generates a reset to the bit
   //reg int_reset;                    //writing 0 this bit in the status register
                                     //generates a reset to the bit
                                     
   //address signal
   reg [2:0]address;               
   
   //receive data reg
   reg [7:0]spirr;                   //data received from SPI bus
   
   //control reg signal
   reg inten;                        //interrupt enable
   
   //status reg signal
   reg dt;                           //data transferring bit
   //reg spierr;                       //spi error bit
   reg bb;                           //bus busy bit
   
   reg [1:0]state,next_state;
   
   //biodirectional signal line
   reg intn;
   reg spi_en;
   reg start_ctrl;
   reg [7:0]spiss;
   //reg tx_empty_rst;
   //reg rec_full_rst;
   reg [1:0]clkdiv_ctrl;
   reg cpha_ctrl;
   reg cpol_ctrl;
   reg [7:0]spitx;
   reg rcv_cpol;
   
   assign int_n=intn;
   assign spien=/*~spien_reset?spien_reset:*/spi_en;
   assign start=start_set?start_set:start_ctrl;
   assign spissr=spiss;
   //assign tx_empty_reset=tx_empty_rst;
   //assign rec_full_reset=rec_full_rst;
   assign clkdiv=clkdiv_ctrl;
   assign cpha=cpha_ctrl;
   assign cpol=cpol_ctrl;
   assign spitr=spitx;
   assign rec_cpol=rcv_cpol;
   
   //assign spi_err=spierr;
   assign spi_bb=bb;
   
   //biodirectional data bus
   assign data=(data_oe==1)?data_out:8'bzzzzzzzz;
   
   always @(wr_n,data)
      if (!wr_n)
         data_in<=data;
      else data_in<=8'b00000000;
      
   
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            state<=idle;
            //next_state<=idle;
         else state<=next_state;
      end
      
   always @(state,spi_config,rd_n,wr_n)
      begin
         //data_oe<=0;
         case (state)
            idle: begin
                     if (spi_config)
                        next_state<=addr_decode;
                     else next_state<=idle;
                  end
            addr_decode: begin
                            if (rd_n^wr_n)
                               next_state<=data_trs;
                            else next_state<=idle;
                         end
            data_trs: next_state<=end_cycle;
            end_cycle: begin
                          if ((!spi_config)&(rd_n&wr_n))
                             next_state<=idle;
                          else next_state<=end_cycle;
                       end
            default: next_state<=idle;
         endcase
      end
      
   //addr_reg
   always @(spi_config,addr)
      if (spi_config) address<=addr;
      else address<=8'b00000000;
      
   always @(posedge clk or negedge reset)
      begin
         if(!reset)
            begin
               ctrl_en<=0;
               stat_en<=0;
               ssr_en<=0;
               tr_en<=0;
               rr_en<=0;
               
               //status reg
               //spierr_reset<=0;
               //int_reset<=0;
               
               //control reg
               spi_en<=0;
               inten<=0;
               start_ctrl<=0;
               clkdiv_ctrl<=2'b00;
               cpha_ctrl<=0;
               cpol_ctrl<=0;
               rcv_cpol<=0;
               
               //slave select reg
               spiss<=8'b00000000;
               
               //transmit data reg
               spitx<=8'b00000000;
               //tx_empty_rst<=0;
               
               //receive data reg