spi_interface.v

a verilog prigram for SPI

module spi_interface(clk,sck,reset,clkdiv,cpha,cpol,miso,mosi,
                     rec_cpol,tx_empty,tx_empty_reset,tx_data,
                     rec_full,rec_full_reset,ss_n_int,ss_n,
                     /*ss_in_int,ss_in_n,*/ss_mask_reg,start,done,
                     rec_data,rec_load);
                     
   input clk,reset,cpha,cpol,miso,rec_cpol,tx_empty_reset,
         rec_full_reset,/*ss_in_n,*/start;
   input [1:0]clkdiv;
   input [7:0]ss_mask_reg,tx_data;
   output mosi,rec_full,done;
   output [7:0]rec_data,ss_n;
   inout sck,rec_load,/*ss_in_int,*/ss_n_int,tx_empty;
   
   wire clk0mask,clk1mask,sclk_int_bufin,sclk_int_bufout0,sclk_int_bufout,
        sclk_int_re,sclk_int_fe,sck_int_re,sck_int_fe,
		  sclk_re,sclk_fe,xmit_load,shift_en_out,shift_en_in;
   
   clk_gen clk_logic(.clk(clk),.reset(reset),.clkdiv(clkdiv),
                     .cpha(cpha),.cpol(cpol),.clk0_mask(clk0mask),
                     .clk1_mask(clk1mask),/*.ss_in_int(ss_in_int),*/
                     .sck_1(sclk_int_bufin),.sck_int_re(sclk_int_re),
                     .sck_int_fe(sclk_int_fe),.sck_re(sclk_re),
                     .sck_fe(sclk_fe),.sck(sck));
                     
   tx_shift xmit_shift(.sclk(sclk_int_bufin),.sys_clk(clk),.reset(reset),
                       .data_in(tx_data),.load(xmit_load),.mosi(mosi),
                       .shift_in(shift_en_out),.shift_en(shift_en_in)/*,
                       .ss_in_int(ss_in_int)*/);
                       
   rec_shift rcv_shift(.sclk(sck),.reset(reset),.cpol(cpol),
                       .rec_cpol(rec_cpol),/*.sclk_re(sclk_re),
                       .sclk_fe(sclk_fe),*/.shift_en(ss_n_int),
                       .miso(miso),.rec_load(rec_load),
                       .data_out(rec_data)/*,.ss_in_int(ss_in_int)*/);
                       
   spi_controller spi_ctrl(.clk(clk),.reset(reset),.sck_int(sclk_int_bufout),
                           .sck_int_re(sck_int_re),.sck_int_fe(sck_int_fe),
                           .sck_re(sclk_re),.sck_fe(sclk_fe),.cpha(cpha),
                           .cpol(cpol),.tx_empty(tx_empty),.tx_load(xmit_load),
                           .tx_shift(shift_en_in),.tx_empty_reset(tx_empty_reset),
                           .rec_full(rec_full),.rec_full_reset(rec_full_reset),
                           .rec_load(rec_load),.clk0_mask(clk0mask),.clk1_mask(clk1mask),
                           .start(start),.done(done),.ss_n_int(ss_n_int),.ss_n(ss_n),
                           .ss_mask_reg(ss_mask_reg)/*,.ss_in_int(ss_in_int),.ss_in_n(ss_in_n)*/);
                           
   nand nand0(shift_en_out,shift_en_in,shift_en_in);
   
   buf buf0(sclk_int_bufout0,sclk_int_bufin);
	buf buf1(sclk_int_bufout,sclk_int_bufout0);
	buf buf2(sck_int_re,sclk_int_re);
	buf buf3(sck_int_fe,sclk_int_fe);
   
endmodule