spi_master_interface_bt.v

a verilog prigram for SPI

module spi_master_interface_bt(clk,reset,spi_start,data,
                               data_byte,data_byte_int,
                               tran_done,load_rr,miso,
                               rec_data,ram_temp);
                               
   input clk,reset;
   output spi_start;
   output [31:0]data;
   output [1:0]data_byte;
   input [1:0]data_byte_int;
   input tran_done;
   input load_rr;
   output miso;
   input [7:0]rec_data;
   output [7:0] ram_temp;
   wire [7:0] ram_temp;
   
   reg spi_start;
   reg [31:0]data;
   reg [1:0]data_byte;
   reg [7:0]ram [3:0];
   reg miso;
   reg [1:0]j;
   
   reg [3:0]state,next_state;
   
   parameter idle=0,tran_id=1,end_id=2,tran_data0=3,
             tran_data1=4,tran_data2=5,tran_data3=6,
             tran_data4=7,end_tran=8;
   
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            state<=idle;
         else state<=next_state;
      end

   always @(state,tran_done)
      begin
         case (state)
            idle: next_state<=tran_id;
            tran_id: begin
                        if (tran_done)
                           next_state<=end_id;
                        else next_state<=tran_id;
                     end
            end_id: next_state<=tran_data0;
            tran_data0: begin
                           if (tran_done)
                              next_state<=tran_data1;
                           else next_state<=tran_data0;
                        end
            tran_data1: next_state<=tran_data2;
            tran_data2: begin
                           if (tran_done)
                              next_state<=tran_data3;
                           else next_state<=tran_data2;
                        end
            tran_data3: next_state<=tran_data4;
            tran_data4: begin
                           if (tran_done)
                              next_state<=end_tran;
                           else next_state<=tran_data4;
                        end
            end_tran: next_state<=end_tran;
            default: next_state<=idle;
         endcase
      end
      
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            begin
               spi_start<=0;
               data_byte<=0;
               data<=32'b0;
            end
         else
            begin
               case (next_state)
                  idle: spi_start<=0;
                  tran_id: begin
                              data[7:0]<=8'b11010011;
                              data_byte<=0;
                              spi_start<=1;
                           end
                  end_tran: spi_start<=0; 
                  tran_data0: begin
                                 data[7:0]<=8'b01000001;
                                 data[15:8]<=8'b10101100;
                                 data[23:16]<=8'b11001100;
                                 data[31:24]<=8'b01100001;
                                 data_byte<=3;
                                 spi_start<=1;
                              end
                  tran_data1: begin
                                 data[7:0]<=8'b00100000;
                                 data[15:8]<=8'b11001000;
                                 data[23:16]<=8'b11001100;
                                 data[31:24]<=8'b11000011;
                                 data_byte<=3;
                              end
                  tran_data2: spi_start<=1;
                  tran_data3: begin
                                 data[7:0]<=8'b11001100;
                                 data[15:8]<=8'b01011011;
                                 data[23:16]<=8'b01110111;
                                 data[31:24]<=8'b00000000;
                                 data_byte<=1;
                              end
                  tran_data4: spi_start<=1;
                  end_tran: spi_start<=0;
                  default: begin spi_start<=0;data<={32{1'b1}}; end
               endcase
            end
      end
            
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            begin
               ram[0]<=8'b00000000;
               ram[1]<=8'b00000000;
               ram[2]<=8'b00000000;
               ram[3]<=8'b00000000;
            end
         else 
			if (load_rr & spi_start)
            ram[data_byte_int]<=rec_data;
      end

	  assign ram_temp = ram[data_byte_int];
      
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            begin
               miso<=0;
               j<=0;
            end
         else if (j==3)
                 begin
                    miso<=~miso;
                    j<=0;
                 end
              else j<=j+1;
      end
      
endmodule