clk_gen.v

a verilog prigram for SPI

module clk_gen(clkdiv,cpha,cpol,clk0_mask,clk1_mask,sck_1,
               sck_int_re,sck_int_fe,sck_re,sck_fe,/*ss_in_int,*/
               sck,clk,reset);
               
   //mcu interface
   input [1:0]clkdiv;                  //sets the clock divisor for sck clock
   input cpha;                         //sets clock phase for output sck clock
   input cpol;                         //sets clock polarity for output sck clock
   
   //spi interface
   input clk0_mask;                    //clock mask for sck when cpha=0
   input clk1_mask;                    //clock mask for sck when cpha=1
   output sck_1;                       //internal sck created from dividing system clock
   output sck_int_re;                  //rising edge of internal sck
   output sck_int_fe;                  //falling edge of internal sck
   output sck_re;                      //rising edge of external sck
   output sck_fe;                      //falling edge of external sck 
   //input ss_in_int;                    //another master is on the bus
   
   //external spi interface signals
   output sck;                         //sck as determined by cpha, cpol, and clkdiv

   input clk;
   input reset;
   
   reg sck_int;                        //version of sck when CPHA=1
   reg sck_0;                          //version of sck when CPHA=0
   reg sck_out;                        //sck to be output if SS_IN_INT is not asserted
   reg sck_int_delay;                  //sck_int delayed one clock for edge detection
   reg sck_out_delay;                  //sck_out delayed one clock for edge detection
   
   wire cnt_en,cnt_clr;
   wire [4:0]qout;

	wire sck_in;
   
   counter_5bit cnt_5(.clk(clk),.clr(cnt_clr),.cnt_en(cnt_en),
                      .q(qout));
                      
   assign cnt_en=1;
   assign cnt_clr=reset/*&ss_in_int*/?1:0;
   
   assign sck_int_re=sck_int&(~sck_int_delay); //generate rising edge of sck_int
   assign sck_int_fe=(~sck_int)&sck_int_delay; //generate falling edge of sck_int
   
   assign sck_1=sck_int&clk1_mask;             
   
   assign sck_re=sck_out&(~sck_out_delay);     //generate rising edge of sck_out
   assign sck_fe=(~sck_out)&sck_out_delay;     //generate falling edge of sck_out

   assign sck_in=/*ss_in_int?*/sck_out/*:1'bz*/;
                      
   //generate sck_int
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            sck_int<=0;
         else
            begin
               case (clkdiv)
                  2'b00: sck_int<=qout[1];
                  2'b01: sck_int<=qout[2];
                  2'b10: sck_int<=qout[3];
                  2'b11: sck_int<=qout[4];
                  default: sck_int<=0;
               endcase
            end
     end
     
   //generate sck_int_delay for generating rising edge and falling edge of sck_int 
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            sck_int_delay<=0;
         else sck_int_delay<=sck_int;
      end
      
   //generate sck_0
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            sck_0<=0;
         else if (!clk0_mask)
                 sck_0<=0;
              else
                 begin
                    case (clkdiv)
                       2'b00: sck_0<=~qout[1];
                       2'b01: sck_0<=~qout[2];
                       2'b10: sck_0<=~qout[3];
                       2'b11: sck_0<=~qout[4];
                       default: sck_0<=0;
                    endcase
                 end
      end
      
   //generate sck_out
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            sck_out<=0;
         else
            begin
               case ({cpha,cpol})
                  2'b00: sck_out<=sck_0;
                  2'b01: sck_out<=sck_1;
                  2'b10: sck_out<=~sck_0;
                  2'b11: sck_out<=~sck_1;
                  default: sck_out<=0;
               endcase
            end
      end
      
   //generate sck_out_delay
   always @(posedge clk or negedge reset)
      begin
         if (!reset)
            sck_out_delay<=0;
         else sck_out_delay<=sck_out;
      end



	buf (sck,sck_in);
      
endmodule